N. Chang

Publications (1)0 Total impact

• Source

  Available from: stanford.edu

  Conference Proceeding: On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

  Xiaoning Qi, Gaofeng Wang, Zhiping Yu, R.W. Dutton, Tak Young, N. Chang
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  ABSTRACT: On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise
  Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000; 02/2000