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ABSTRACT: As CMOS technology is scaled, the design of a robust electrostatic-discharge (ESD) protection circuit that is transparent to the main circuit is becoming more challenging. For high- frequency applications where minimum parasitic capacitance is required, diodes along with clamps are a popular ESD protection method. The main challenge in the clamp design is to keep the clamp in "on" mode for the whole ESD event while minimizing area and avoiding false triggering. In this paper, a new clamp that uses a flip-flop to turn on the clamp for the complete ESD event is presented. The trigger circuit is able to keep the clamp on for over 2 mus, and this clamp passes a 3-kV HBM ESD stress. Simulation results show that this clamp is immune to false triggering and power supply noise. Furthermore, the stability problem in clamps is addressed, and the new clamp is shown to be immune to oscillation.
IEEE Transactions on Device and Materials Reliability 07/2008; · 1.54 Impact Factor
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ABSTRACT: The increase in process parameter variations and off-state current for deep submicron complementary metal oxide semiconductor (CMOS) technologies makes conventional (single threshold) I<sub>DDQ</sub> testing ineffective. Delta I<sub>DDQ</sub> testing performed at two temperatures for a given test vector and called 'thermal delta I<sub>DDQ</sub> testing' is a more attractive alternative and is investigated by the authors. On the basis of statistical Monte Carlo simulations and industrial data, it is shown that lowering the temperature from 330 K to 280 K results in a more than times100 reduction of Iddq mean value and approximately times15 reduction of Iddq standard deviation of defect-free 0.18 m CMOS circuits.
IET Circuits Devices & Systems 01/2008; · 0.55 Impact Factor
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ABSTRACT: Impact of ESD protection devices on circuit operation is very important in gigahertz applications. In this paper, the impact of different ESD protection methodologies on CML drivers is discussed. ESD protection is provided using MOSFET and SCR devices. Study of the interaction between driver and ESD protection circuit shows that jitter is very sensitive to parasitics of ESD protection circuits. Furthermore, an analysis shows that substrate-triggering has less impact on jitter compared to gate-coupling.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: A novel clamp is presented that uses a CMOS thyristor to turn on the clamp at the ESD event. This clamp is immune to false triggering and power supply noise. Furthermore, the instability of clamps is analyzed and the new clamp is shown to have immunity to oscillation.
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD; 10/2007
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ABSTRACT: As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-μm bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15°C and by 7°C in 0.09-μm SOI and bulk CMOS technologies, respectively.
IEEE Transactions on Device and Materials Reliability 04/2006; · 1.54 Impact Factor
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ABSTRACT: As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.
Microelectronics Journal. 01/2006;
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ABSTRACT: As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free LVTSCR-based protection circuit is proposed. It can be reliably used in sub-0.18 μm CMOS technologies and burn-in environment. The proposed ESD circuit has higher holding voltage by 1.5× than the conventional LVTSCR structure at burn-in temperature. Under 3 kV HBM ESD stress, the developed LVTSCR-based protection circuit has the voltage peak less than the conventional LVTSCR structure and GG-MOSFET by 2× and 1.25×, respectively.
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on; 04/2005
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ABSTRACT: This article describes how CMOS IC technology scaling impacts semiconductor burn-in and burn-in procedures. Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss of good parts during burn-in. The paper discusses the effect of junction temperature on device reliability, aging, and burn-in procedure optimization. The effect of device thermal runaway and the requirements it forces on commercial burn-in ovens, device package, and device cooling are also described.
IEEE Transactions on Device and Materials Reliability 07/2004; · 1.54 Impact Factor
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ABSTRACT: In deep sub-micron technologies, increased standby leakage current in high performance processors results in increased junction temperature. Elevated junction temperature causes further increase on the standby leakage current. The standby leakage current is expected to increase even more under the burn-in environment leading to still higher junction temperature and possibly the thermal runaway. In this paper we investigate the thermal management of high performance processors during burn-in.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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ABSTRACT: In deep sub-micron CMOS technologies, increased standby current in high performance processors results in increased junction temperature. This elevated temperature has a positive feedback on the standby current. If the temperature is not controlled, it may lead to thermal runaway. In this paper we investigate the thermal management of high performance chips in the burn-in environment.
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on; 12/2003
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ABSTRACT: Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss during burn-in. The authors estimate the increase in junction temperature with technology scaling. Their research shows that under normal operating conditions, the junction temperature is increasing 1.45×/generation. The increase in junction temperature under the burn-in condition was found to be exponential. The range of optimal burn-in voltage and temperature is reduced significantly with technology scaling.
IEEE Transactions on Semiconductor Manufacturing 12/2003; · 0.72 Impact Factor
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ABSTRACT: Comparative analysis of the conventional 6T and recently proposed loadless 4T CMOS SRAM cells is performed. Based on HSPICE simulations for 0.18-μm technology, we compared the stability of the aforementioned cells to temperature and process (V<sub>TH</sub>, L<sub>eff</sub>, T<sub>OX</sub>) variations as well as the cells robustness in low-voltage operation. We found that at V<sub>DD</sub> = 1.2 V the loadless 4T cell has a 20% higher static noise margin (SNM) and 1.5 times lower sensitivity to the V<sub>TH</sub> fluctuations than the 6T cell. On the other hand, the 4T cell has a stronger read current degradation at reduced V<sub>DD</sub>. The analytical model for SNM calculation of the loadless 4T CMOS SRAM cell has been developed.
Integrated Reliability Workshop Final Report, 2002. IEEE International; 11/2002
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ABSTRACT: In this paper, the impact of gate induced drain leakage (GIDL) on
the overall leakage of submicrometer VLSI circuits is studied. GIDL
constitutes a serious constraint, with regards to off-state current, in
scaled down complimentary metal-oxide-semiconductor (CMOS) devices for
DRAM and/or EEPROM applications. Our research shows that the GIDL
current is also a serious problem in scaled CMOS digital VLSI circuits.
We present the experimental and simulation data of GIDL current as a
function of 0.35-μm CMOS technology parameters and layout of CMOS
standard cells. The obtained results show that a poorly designed
standard cell library for VLSI application may result in extremely high
leakage current and poor yield
IEEE Transactions on Semiconductor Manufacturing 03/2002; · 0.72 Impact Factor
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ABSTRACT: The leakage power is expected to increase with scaling of CMOS technology. The increased leakage is a strong function of the elevated temperature and voltage stress. As a consequence; under the burn-in (BI) conditions the elevated leakage power may cause increased post burn-in fallout. In this paper the impact of elevated leakage and technology scaling in burn-in environment on post BI yield is analyzed. We have also shown that to maintain a constant post-BI yield loss, the burn-in temperature should go down by 10°C for each technology generation. We also show that at static burn-in conditions, the die temperature is increased exponentially and range of optimal stressed voltage and temperature for fixed post burn-in yield loss is reduced significantly, when CMOS technology is aggressively scaled down.
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on; 02/2002
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ABSTRACT: In this paper, the impact of gate induced drain leakage (GIDL) on
overall leakage of submicron VLSI circuits is studied. GIDL constitutes
a serious constraint, with regards to off-state current, in scaled down
CMOS devices for DRAM and/or EEPROM applications. Our research shows
that the GIDL current is also a serious problem in scaled CMOS digital
VLSI circuits. We present the experimental and simulation data of GIDL
current as a function of 0.35 μm CMOS technology parameters and
layout of CMOS standard cells. The obtained results show that a poorly
designed standard cell library for VLSI application may result in
extremely high leakage current and poor yield
Integrated Reliability Workshop Final Report, 2001. 2001 IEEE International; 02/2001
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ABSTRACT: It is well known that classical fault models (stuck-at, stuck-open, stuck-on) cover only partially the spectrum of failures in today's integrated circuits (IC). Some realistic failures occurring in logic circuits have to be considered at the physical level and include its electrical behavior. Among these failures, gate-oxide short, floating gate and bridging fault types may produce intermediate voltages with difficult interpretations at logic level. This work investigates the influence of a bridging fault (BF) between two interconnection lines on the logic margin and logic swing of an IC and the sensitivity of digital ICs realized on four different technologies (0.25 μm, 0.35 μm, 0.5 pm. 1.5 μm) to bridging faults. Several circuits, including D flip-flops and ISCAS benchmark circuits, were analyzed to find out the impact of technology scaling on BF defects detection. In this work we show that the sensitivity of an IC to BF is increased with technology scaling. The testing methodology was based on the use of voltage, temperature and frequency as parameters, which influence on the behavior of an IC with BF
Defect Based Testing, 2000. Proceedings. 2000 IEEE International Workshop on; 02/2000
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[show abstract]
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ABSTRACT: It is well known that classical fault models (stuck-at,
stuck-open, stuck-on) cover only partially the spectrum of failures in
today's integrated circuits (IC). Some realistic failures occurring in
the logic circuits have to be considered at physical level and include
its electrical behavior. Among these failures, gate-oxide short,
floating gate and bridging fault types may produce intermediate voltages
difficult to interpret at logic level. This work investigates the
influence of bridging faults (BF) between two interconnection lines on
logic margin and logic swing of ICs and the sensitivity of ICs realized
on four different technologies (0.25 μm, 0.35 μm, 0.5 μm, 1.5
μm) to bridging faults. In this work we show that the sensitivity of
ICs to BF is increased with the technology scaling. The testing
methodology was based on the use of voltage, temperature and frequency
as parameters, which influence the behavior of ICs with BF
Electrical and Computer Engineering, 2000 Canadian Conference on; 02/2000
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Test Conference, 2003. Proceedings. ITC 2003. International;
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ABSTRACT: Silicon controlled rectifiers (SCRs) are used extensively in high frequency applications. To reduce their first breakdown voltage, they are used with different triggering mechanisms. In this paper, a novel ESD protection device is proposed that can reduce the first breakdown voltage of SCR to 3V without any extra triggering devices.
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International;
