[Show abstract][Hide abstract] ABSTRACT: In this paper, we propose a method for extracting the spectral information of a multigigahertz jittery signal without using an ideal reference clock. This method utilizes existing on-chip single-shot period measurement techniques to measure single periods of a multigigahertz signal for analysis. Utilizing the same sampling and measuring principle, we propose another less computationally intensive method, based on the derivative principle, to extract only the random jitter component of the signal. To perform analysis on higher frequency signals, both methods are extended to measures multiple signal periods, instead of a single period, at each sampling. These methods do not require an ideal sampling clock, nor any additional measurement beyond existing techniques. Experimental results based on simulation show that these methods can accurately estimate the sinusoidal and random jitters of a multigigahertz signal. Extracted values can be used for estimating the bit-error rate of serial communication systems.
Circuits and Systems I: Regular Papers, IEEE Transactions on 10/2008; 55(8-55):2263 - 2272. DOI:10.1109/TCSI.2008.918235 · 2.40 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: High performance serial communication systems often require the bit error rate (BER) to be at the level of 10<sup>-12</sup> or below. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems cost-effectively. We propose a new technique for accurate and efficient estimation of the BER. The proposed technique estimates the BER based on the spectral information of jitter and the characteristics of the clock and data recovery circuit. The method can significantly reduce the production test time for BER testing. Simulation results demonstrate the potential usefulness of the method.
Test Conference, 2004. Proceedings. ITC 2004. International; 11/2004
[Show abstract][Hide abstract] ABSTRACT: In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method utilizes existing on-chip single-shot period measurement techniques to sample and measure the period of multiple cycles of the multi-gigahertz periodic signal for spectral analysis. Since measurements are made on the period of multiple cycles, but not on the period of a single cycle, a lower-speed timing measurement circuitry can be used to measure a higher-speed signal. Therefore, the proposed solution is scalable for even higher-speed signals. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results based on simulation show that this method can accurately estimate the sinusoidal and random jitters of a multi-gigahertz signal.
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE; 05/2004
[Show abstract][Hide abstract] ABSTRACT: In this paper, we propose a simple technique for estimating the standard deviation of a Gaussian random jitter component in a multi-gigahertz signal. This method may utilize existing on-chip single-shot period measurement techniques to measure the multi-gigahertz signal periods for the estimation. This method does not require an external sampling clock, or any additional measurement beyond existing techniques. Experimental results show that this extraction method can accurately estimate the random jitter variance in a multi-gigahertz signal even with the presence of a few hundred-hertz sinusoidal jitter components.
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings; 03/2004
[Show abstract][Hide abstract] ABSTRACT: Sigma-delta modulators are commonly used in high-resolution analog-to-digital converters (ADCs). Testing this type of modulator requires a high-resolution test stimulus, which is difficult to generate. A new architecture for the modulator is proposed so that its performance can be determined using only digital test stimulus. This architecture does not need analog test stimuli, which is prone to distortion/noise while setting up the high-resolution modulator for testing. Simulation results show that this technique is capable of accurately determining the performance of a second-order sigma-delta modulator ADC.
Circuits and Systems I: Regular Papers, IEEE Transactions on 02/2004; 51(1-51):206 - 213. DOI:10.1109/TCSI.2003.821305 · 2.40 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper proposes a mixed-signal built-in self-test (BIST) architecture based on a second-order delta-sigma modulator. This modulator, which incorporates design-for-testability (DfT) circuitry, is capable of testing/characterizing itself using digital stimulus. This characteristic is attractive for implementing the modulator as an on-chip analog signal analyzer. When applied for mixed-signal BIST, the modulator-based analog signal analyzer is first characterized using digital stimulus. Then the analyzer is utilized to characterize the stimulus generator in the BIST application. Some critical implementation issues of the BIST architecture are also discussed.
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific; 02/2003
[Show abstract][Hide abstract] ABSTRACT: This paper presents a design of the built-in high resolution signal generator for testing analog-to-digital converter (ADC) and digital-to-analog converter (DAC). The sigma-delta demodulator scheme is used in the design to generate on-chip high accurate stimulus. We discuss the issues on the generation of all the required stimuli using the same circuitry and other issues on implementing this scheme. Our signal generator can be applied to test the embedded 13-bit ADC and DAC in asymmetry digital subscriber line system on a chip (ADSL SoC).
VLSI Technology, Systems, and Applications, 2003 International Symposium on; 02/2003
[Show abstract][Hide abstract] ABSTRACT: Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is difficult to generate. This paper proposes a novel and robust technique to determine the performance of the modulator, which incorporates simple design-for-testability circuitry. This technique requires only digital stimulus to test the modulator. Hence, it is suitable as an analog signature analyzer used in built-in self-test applications. Simulation results show that this technique is capable of accurately determining the performance of a second-order delta-sigma modulator ADC.
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE; 02/2002
[Show abstract][Hide abstract] ABSTRACT: In this paper we present a BIST scheme for testing on-chip A/D and D/A converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation-5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings; 02/2000
[Show abstract][Hide abstract] ABSTRACT: In this paper, we characterize and evaluate the effectiveness of a pseudo-random-based implicit functional testing technique for analog and mixed-signal circuits. The analog test problem is transformed into the digital domain by embedding the device-under-test (DUT) between a digital-to-analog-converter and an analog-to-digital converter. The pseudo-random testing technique uses band-limited digital white noise (pseudo- random-patterns) as input stimulus. The signature is constructed by computing the cross-correlation between the digitized output response and the pseudo-random input sequence. We have implemented a DSP-based hardware testbed to evaluate the effectiveness of the pseudo-random testing technique. Our test results show that we can achieve close to 100% yield and fault coverages by carefully selecting only two cross - correlation samples. Noise level and total harmonic distortion below 0.1% and 0.5%, respectively, do not affect the classification accuracy.
18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada; 01/2000