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ABSTRACT: The amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT)-based nonvolatile transparent Flash memory devices were fabricated with gold (Au) nanocrystal storage layer. The performance and the reliability of transparent memory devices have been characterized by experiment and technology computer-aided design simulation. This memory device shows a large-enough memory window ΔV = 4.7 V at the program/erase (P/E) voltage V <sub>PGM</sub>/ V <sub>ERS</sub> = 35/-35 V for the P/E time T <sub>PGM</sub>/ T <sub>ERS</sub> = 3/25 s. The memory window was kept almost the same after 1050 P/E cycles; however, the center voltage of the memory window ( VC ) was shifted in a negative direction. The cycling effect was explained by the change in the density of states (DOS) and the acceptor-like interface-trap density D <sub>itA</sub>( E ) in the a-IGZO channel layer with increasing P/E cycles. The main mechanism for the change in VC was found to be the accelerated injection of holes into the gate insulator due to the energy band bending during the erase operation.
IEEE Transactions on Electron Devices 12/2011; · 2.32 Impact Factor
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ABSTRACT: In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt , the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/ f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/ f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/ f model developed is discussed.
IEEE Transactions on Nanotechnology 06/2011; · 2.29 Impact Factor
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Rock-Hyun Baek,
Chang-Ki Baek,
Sang-Hyun Lee,
Sung Dae Suk,
Ming Li,
Yun Young Yeoh,
Kyoung Hwan Yeo,
Dong-Won Kim,
Jeong-Soo Lee, D.M. Kim,
Yoon-Ha Jeong
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ABSTRACT: Presented in this letter are the C - V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C - V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated using C - V data, and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance R <sub>sd</sub>. These observed data are compared with the data from planar MOS capacitor.
IEEE Electron Device Letters 03/2011; · 2.85 Impact Factor
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ABSTRACT: The series resistance, R <sub>sd</sub> in silicon nanowire FETs (Si-NWFET) is extracted unambiguously, using the Y -function technique, in conjunction with the drain current and transconductance data. The volume channel inversion in Si-NWFET renders the charge carriers relatively free of the surface scattering and concomitant degradation of mobility. As a result, the Y -function of Si-NWFET is shown to exhibit a linear behavior in strong inversion, thereby enabling accurate extraction of R <sub>sd</sub>. The technique is applied to nanowire devices with channel lengths 82, 86, 96, 106, 132, and 164 nm, respectively. The extracted R <sub>sd</sub> values are shown nearly flat with respect to the gate voltage, as expected from Ohmic contacts but showed a large variation for all channel lengths examined. This indicates the process parameters involved in the formation of series contacts vary considerably from device to device. The present method only requires a single device for extraction of R <sub>sd</sub> and the iteration procedure for data fitting is fast and stable.
IEEE Transactions on Nanotechnology 04/2010; · 2.29 Impact Factor
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ABSTRACT: This paper presents the depth profile of oxide trap density, extracted from the dual gate processed thermally grown oxide in NO ambient and remote plasma nitrided oxides by using multifrequency and multitemperature charge pumping technique in conjunction with the tunneling model of trapped charges. Nitrided oxide is widely used to improve the reliability of nanoscale MOSFETs because it can decrease the degradation of gate oxide due to the generation of traps therein. Based on the measurement, the optimum nitrogen concentration in such typical nitrided process is discussed in correlation with the gate oxide thickness for nanoscale CMOSFETs.
IEEE Transactions on Nanotechnology 10/2009; · 2.29 Impact Factor
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ABSTRACT: The interaction of an organic molecule with metal electrodes possessing various work functions and atomic species is investigated by ab initio calculations. The results indicate that the chemical nature of the atomic species of the electrode and interface geometry elicit significant changes in both the physical structure and electronic properties at distances as great as 1 nm from the interface. Also, the metal electrodes having similar work functions contacting the same molecule give rise to different transmission profiles, thereby leading to widely varying I - V characteristics.
IEEE Transactions on Nanotechnology 02/2009; · 2.29 Impact Factor
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ABSTRACT: Presented herein are the first-principle calculations of the transport and other pertinent electronic properties of metal contacted semiconducting carbon nanotubes (CNTs). The investigation is focused on elucidating access resistance as a function of the work function difference and the chemical nature of the metal atomic species. Our results show that, for simple end-contact geometries, the Fermi level position within the gap differs between palladium-contacted CNTs and gold-contacted CNTs. This is interesting since both of these metals possess similar work functions. The role of the metal-CNT coupling is examined in light of the resulting - behavior of the system.
IEEE Transactions on Nanotechnology 04/2008; · 2.29 Impact Factor
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ABSTRACT: In the original article by B. Kim (see ibid., vol. 53, no. 12, p. 3012-3019, Dec. 2006) the biography for Dr. Kinam Kim was out of date. A more current one is given
IEEE Transactions on Electron Devices 05/2007; 54(4):893-893. · 2.32 Impact Factor
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ABSTRACT: The interaction of an organic molecule with different metal electrodes is investigated by ab initio calculations. The results show that the chemical nature of the electrode atomic species and interface geometry elicit significant geometrical changes in the molecule at distances as great as 1 nm from the interface together with substantial modification of the electronic properties. Also, the orientations of the metal electrode-molecule interface give rise to significant changes in the electron density profile of the molecule. Thus, metal electrodes possessing similar work functions give rise to different conductance characteristics when contacted to the same molecule.
Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE; 11/2006
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J B Choi,
S H Seo,
J U Lee,
G C Kang,
S W Kim,
K S Roh,
K Y Kim,
C H Lee,
S Y Lee,
H T Kim,
D H Kim,
K S Min,
D J Kim,
D W Kang,
J K Rhee, D M Kim
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ABSTRACT: In this paper, a novel characterization technique is presented to quantitatively extract the energy distribution of interface states in the gate-to-drain overlapped region of MOSFETs. Optical excitation with a sub-bandgap optical power (E ph = 0.95 eV < Eg,Si = 1.12 eV) is applied over the MOSFETs and the gate-induced drain leakage (GIDL) current, named the optically-induced GIDL, and the energy distribution of interface states in the gate-to-drain overlapped region of MOSFETs can be extracted. The increased drain leakage current under sub-bandgap optical illumination is expected to be predominantly caused by optical trap-assisted tunneling (optical GIDL current, IOT AT = ∆IGIDL = ID,opt – I D,dark). Combining analytical models for the GIDL current, which is increased only by trap-assisted tunneling under sub-bandgap photonic excitation, we extracted interface-state density in the gate-to-drain overlapped region, excluding the band-to-band tunneling current in the off-state drain leakages in MOSFETs. Our optical GIDL current measurement is shown to be in good agreement with the results of the charge pumping and photonic gated diode method (PGDM) results for interface states in MOSFETs.
Journal- Korean Physical Society 11/2006; 4920(73). · 0.45 Impact Factor
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ABSTRACT: The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.
IEEE Electron Device Letters 04/2006; · 2.85 Impact Factor
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H.T. Kim,
J.B. Choi,
J.U. Lee,
S.W. Kim,
G.C. Kang,
D.J. King,
K.S. Min,
D.W. Kang, D.M. Kim,
I.C. Nam,
K.S. Kim,
K.H. Kim
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ABSTRACT: This work presents a new method for extracting the intrinsic source and drain resistances in MOSFETs. This is based on the open-collector method in the parasitic bipolar junction transistor (sourcebody-drain) parallel to the MOSFET. By using the Ebers-Moll equivalent model for bipolar junction transistors, the source and drain resistances are extracted separately excluding the resistance formed by the LDD region. Combining the current-voltage characteristics under a linear operation mode of MOSFETs, we can also extract the LDD-parts in the total resistance.
Electronics Letters 07/2005; · 0.96 Impact Factor
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ABSTRACT: Presented herein is an efficient simulation technique enabling systematic investigation of the soft programming over-erased flash EEPROM cells. The simulation provides a method by which to find the optimal soft programming technique for given current. The method requires only the cell performance data and allows investigation of the soft programming under various bias conditions. In principle, the methodology can also be used to investigate the programming and erase operations.
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004
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T E Kim,
H T Kim,
H T Shin,
H S Park,
K S Kim,
I C Nam,
K H Kim,
J B Choi,
J U Lee,
S W Kim,
G C Kang,
D J Kim,
K S Min,
D W Kang, D M Kim
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ABSTRACT: A sub-bandgap photonic gated-diode method was applied to comparatively extract the energy-dependent, spatial distributions of traps at the SiO2/Si heterojunction interface in MOSFETs before and after electrical stress. The sub-bandgap photonic gated-diode method was also applied to investigate the interface states (Dit, Nit) and the oxide (Qox) trap distributions caused by the channel's hot carrier injection with electrical overstress in an n-MOSFET. An optical source with a sub-bandgap energy less than the silicon bandgap energy (E ph = 0.95 eV < Eg = 1.12 eV) was employed for the photonic characterization of the interface states (Eit) distributed within the photo-responsive energy band (EC -0.95 ≤ Eit ≤ EC) in MOS systems. We obtained Dit,max = 2.5 × 10 13 [1/(cm 2 eV)], Nit,max = 1.65 × 10 14 [1/cm 2 ], and Qox,max = 1.18 × 10 11 [q/cm 2 ]. Through experimental observations with electrical overstress for hot-carrier injection, we observed that the reliability of MOSFETs was dominated more by the interface states than by the oxide trapped charges.
Journal- Korean Physical Society 07/2004; 44:1479-1484. · 0.45 Impact Factor
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H T Shin,
K H Kim,
K S Kim,
I C Nam,
J B Choi,
J U Lee,
S W Kim,
H T Kim,
T E Kim,
H S Park,
G C Kang,
D J Kim,
K S Min,
D W Kang, D M Kim
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ABSTRACT: In this paper, we propose a novel photonic base current analysis method to characterize the inter-face states in heterojunction bipolar transistors (HBTs) by using the photonic I-V characteristics under sub-bandgap photonic excitation. For the photonic current-voltage characterization of HBTs, an optical source with a photon energy less than the bandgap energy of Al0.3Ga0.7As and GaAs (E ph = 0.95 eV < E g,AlGaAs = 1.79 eV & Eg,GaAs = 1.45 eV) is employed for the characterization of the interface states distributed in the photo-responsive energy band (EC -0.95 ≤ Eit ≤ EC) in emitter-base heterojunction at HBTs. The proposed novel method, which is applied to bipolar junction transistors for the first time, is simple, and an accurate analysis of interface traps in HBTs is possible. By using the photonic base-current and the dark-base-current, we qualitatively analyze the interface trap at the Al0.3Ga0.7As/GaAs heterojunction interface in HBTs.
Journal- Korean Physical Society 07/2004; 44:1485-1489. · 0.45 Impact Factor
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M.S. Kim,
I.C. Nam,
H.T. Kim,
H.T. Shin,
T.E. Kim,
H.S. Park,
K.S. Kim,
K.H. Kim,
J.B. Choi,
K.S. Min, D.J. Kim,
D.W. Kang,
D.M. Kim
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ABSTRACT: Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E<sub>ph</sub><E<sub>g</sub>) photonic energy (E<sub>ph</sub>=0.943 eV, P<sub>opt</sub>=+5 dBm), which is less than the silicon bandgap (E<sub>g</sub>=1.12;eV), is employed for the optical subthreshold current characterization of interface states in the photoresponsive energy band. We applied the OSCM method under a subbandgap photonic excitation to MOS systems with a poly-Si gate and verified a U-shaped distribution of interface trap density D<sub>it</sub>=10<sup>10</sup>∼10<sup>12</sup> eV<sup>-1</sup>cm<sup>-2</sup> for n- and p-type MOSFETs with W/L=30 μm/1.2 μm.
IEEE Electron Device Letters 03/2004; · 2.85 Impact Factor
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S.S. Chi,
H.T. Kim,
M.S. Kim,
T.E. Kim,
H.T. Shin,
H.S. Park,
K.H. Kim,
K.S. Kim,
I.C. Nam, D.J. Kim,
K.S. Min,
D.W. Kang,
D.M. Kim
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ABSTRACT: A new sub-bandgap photonic gated-diode method is proposed to extract the energy-dependent and spatial distributions of traps at the SiO<sub>2</sub>/Si interface in MOSFETs. For the photonic current-voltage (I-V) characterisation of MOSFETs, an optical source with a sub-bandgap photon energy less than the silicon bandgap (E<sub>ph</sub>=0.95 eV<E<sub>g</sub>=1.12 eV) is employed for the characterisation of interface states (D<sub>it</sub>) distributed in the photo-responsive energy band (E<sub>C</sub>-0.95≤E<sub>it</sub>≤E<sub>C</sub>) in MOS systems with a polysilicon gate.
Electronics Letters 12/2003; · 0.96 Impact Factor
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ABSTRACT: In this paper, we propose a novel subthreshold current method using the optical current-voltage (I-V) curve for interface-state extraction. The new method is simpler and more accurate than the conventional interface-state extraction methods in MOSFETs. Based on the photonic high-frequency capacitance-voltage response of MOS capacitors and the conventional subthreshold cur-rent method, an improved characterization method is reported for the analysis of interface-states in MOS systems. An optical source with a photonic energy E ph = 0.943 eV (wavelength = 1314.5 nm) is employed for optical subthreshold current characterization of interface-states distributed in the photo-responsive energy-band. By using the optical subthreshold current and dark subthreshold current, we obtained a U-shaped distribution for the interface-trap density (Dit) in N-type and P-type MOSFETs.
Journal- Korean Physical Society 12/2003; 43:878-883. · 0.45 Impact Factor
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ABSTRACT: Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseu-domorphic HEMTs have been investigated under sub-bandgap photonic excitation (hν<E g). Drain (V DS)-, gate(V GS)-, and optical power(P opt)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage (V GS,P) and the onset voltage for the impact ionization (V GS,II) have been extracted and empirical model for their dependence on the V DS and P opt have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characteri-zation, as a function of the optical power with hν=0.799eV, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.
09/2003; 3.
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ABSTRACT: Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.
Electronics Letters 09/2003; · 0.96 Impact Factor
