Marek Kropidłowski

Poznan University of Technology, Posen, Greater Poland Voivodeship, Poland

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Publications (5)5.73 Total impact

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    ABSTRACT: This work is the answer to the so far unsolved problem of generation of integrated circuits topography for current mode circuits. Synthesis methods corresponding to already existing digital methods are proposed. Among others – the following has been shown: a digital adaptation of the row strategy for analog cell design, as well as performance control of the circuits with respect to chip area, power consumption and speed operation. The proposed algorithms are integrated with the already-existing tools for automatic layout generation of analog circuits with behavioral description at the beginning. At each stage of the synthesis process – an architecture description in the VHDL-AMS language was used, which so far has been not useful to synthesize. On the basis of the elaborated expert system, layouts of a filter pair and a filter bank were generated. The circuits were fabricated in TSMC CMOS technology and results of measurements are presented. The elaborated approach makes a contribution to the realization of current mode circuits with complexity not achievable up to now.
    Expert Systems with Applications 04/2015; 42(6). DOI:10.1016/j.eswa.2014.11.048 · 2.24 Impact Factor
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    ABSTRACT: The paper presents expert tools which are elaborated on the basis of synthesis method of lossless nonreciprocal multiport circuits, composed of gyrators and capacitors. The algorithms are written in C++ and the tools compose a user friendly environment for design automation of filters, filter pairs and filter banks. It is possible to design in this environment not only classical structures like Butterworth, Chebyshev, and Cauer (elliptic) filters. The lossless nonreciprocal prototype circuit allows to design more complex filters, including allpass sections necessary to improve filter phase characteristics. However, the most important possibility is to design multiport circuits, especially in the case of not fully determined filter specifications. On each stage of the design process VHDL-AMS is used to describe the circuits. The obtained prototype gyrator-capacitor circuit can be implemented in OTA-C, SC (switched-capacitor) or SI (switched-current) techniques to realize the filter in CMOS technology. In the paper SI technique is used for layout generation of an image filter in order to illustrate the elaborated synthesis algorithms and tools.
    Expert Systems with Applications 04/2014; 41(5):2211-2221. DOI:10.1016/j.eswa.2013.09.019 · 2.24 Impact Factor
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    ABSTRACT: The paper presents a VHDL-AMS based approach to the Switched-Current (SI) Sigma-Delta Modulator design. The prototype VHDL-AMS description, with the help of elaborated EDA tools, is automatically translated into the SI realization. Another tool helps the designer to create the layout. The paper also describes a new current mode comparator, which is used in the design. Postlayout simulation results are presented.
    International Journal of Electronics and Telecommunications 12/2013; 59(4). DOI:10.2478/eletel-2013-0048
  • Radek Rudnicki · Marek Kropidłowski · Andrzej Handkiewicz ·
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    ABSTRACT: The switched-current (SI) technique permits realizing analog discrete-time circuits in standard digital CMOS technology. A very important property of the analog part of a system on a chip is the possibility it offers for realizing some functions of a digital circuit, but with reduced power consumption. In this paper, a low power SI integrator is presented. It is shown that an integrator consuming a fraction of a milliwatt can be designed in 0.35µm CMOS technology with the use of narrow transistor channels, and with the channel length as a design parameter. The impact of the rise/fall time of the clock signal on the integrator operation is observed. It is shown that this effect can be reduced when the proper switch dimensions are taken for the integrator. Analysis and measurements of the integrator noise are presented. The integrator was built with equal size transistors, yielding less sensitivity to variations in production parameters. An experimental chip in 0.35µm CMOS technology was fabricated, and measurements are compared with results obtained during analysis and simulations. In order to verify the properties of the designed integrator experimentally, a first-order filter is built with the use of elementary cells on the chip. Copyright © 2008 John Wiley & Sons, Ltd.
    International Journal of Circuit Theory and Applications 01/2008; 38(5):471 - 486. DOI:10.1002/cta.576 · 1.25 Impact Factor
  • Andrzej Handkiewicz · Marek Kropidłowski · Marcin Łukowiak ·
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    ABSTRACT: The paper describes briefly techniques used in image processing. The computational complexity makes these techniques difficult for real-time hardware implementation. It is shown in the paper that intensively developed field programmable gate arrays can efficiently realize real-time image processing. An example of such implementation, shown in the paper, is a median filtering.