-
[show abstract]
[hide abstract]
ABSTRACT: We have examined the stability of TbScO3 on Si(100) using medium energy ion scattering. At high temperatures the dielectric decomposes into a Tb-rich silicate layer near the substrate, and a Sc-rich layer near the surface. Interfacial SiO2 is consumed in the reaction. We find that Sc2O3 by itself does not react with SiO2 while Tb2O3 readily forms a silicate. This difference in reactivity drives the vertical separation of metal ions. Consideration of the fundamental chemistry of rare-earth scandates suggests that rare-earth scandates are unstable in the presence of SiO2
Applied Physics Letters 11/2010; 97(18):182901-182901-3. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We report the effect of La2O3 capping layers on HfO2/SiO2/Si dielectrics, proposed for use in threshold voltage tuning of field effect transistors. Depth profiling with medium energy ion scattering shows that an initial surface layer of La2O3 diffuses through the HfO2 at elevated temperatures, ultimately converting some of the thin interfacial SiO2 into a silicate. Core-level photoemission measurements indicate that the additional band-bending induced by the La2O3 only appears after diffusion, and the added charge resides between the HfO2 and the substrate.
Applied Physics Letters 11/2009; 95(21):212903-212903-3. · 3.84 Impact Factor
-
M.M. Frank,
V.K. Paruchuri,
V. Narayanan, N. Bojarczuk,
B. Linder,
S. Zafar,
E.A. Cartier,
E.P. Gusev,
P.C. Jamison,
K.L. Lee, [......],
K. Maitra,
X. Wang,
P.M. Kozlowski,
J.S. Newbury,
D.R. Medeiros,
P. Oldiges,
S. Guha,
R. Jammy,
M. Ieong,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: We demonstrate poly-Si/high-k gate stacks suitable for successful implementation in low power technologies. An optimized gate dielectric process was employed to suppress the large pFET threshold voltage shift commonly found with Hf-based gate dielectrics, reducing it to -0.2 V, while preserving pFET and nFET device performance.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
-
E.P. Gusev,
V. Narayanan,
S. Zafar,
C. Cabral Jr,
E. Carrier, N. Bojarczuk,
A. Callegari,
R. Carruthers,
M. Chudzik,
C. D'Emic,
E. Duch,
P. Jamison,
P. Kozlowski,
D. LaTulipe,
K. Maitra,
F.R. McFeely,
J. Newbury,
V. Paruchuri,
M. Steen
[show abstract]
[hide abstract]
ABSTRACT: A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or T<sub>inv</sub>, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates); (ii) high-k dielectric material (HfO<sub>2</sub>, HfO<sub>2</sub>:N, HfSiO, HfSiON, ZrO<sub>2</sub>, Al<sub>2</sub>O<sub>3</sub>); (iii) high-k deposition technique (MOCVD vs. ALD); (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-k layer and poly-Si plays a major role in charge trapping degradation.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
E.P. Gusev,
C. Cabral Jr,
B.P. Under,
Y.H. Kim,
K. Maitra,
E. Carrier,
H. Nayfeh,
R. Amos,
G. Biery, N. Bojarczuk, [......],
H. Ng,
P. Nguyen,
J. Newbury,
V. Paruchuri,
R. Rengarajan,
G. Shahidi,
A. Steegen,
M. Steen,
S. Zafar,
Y. Zhang
[show abstract]
[hide abstract]
ABSTRACT: The key result in this work is that FUSI/HfSi<sub>x</sub>O<sub>y</sub> gate stacks offer both significant gate leakage reduction (due to high-κ) and drive current improvement at T<sub>inv</sub> ∼ 2 nm (due to: (i) elimination of poly depletion effect, ∼ 0.5 nm, and (ii) the high mobility of HfSi<sub>x</sub>O<sub>y</sub>). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)∼ -0.4 V and Vt(NFET) ∼ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V<sub>t</sub> stability) was found in the case of NiSi/ HfSi<sub>x</sub>O<sub>y</sub> compared to the same gate electrode with HfO<sub>2</sub> dielectric.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
E. Cartier,
V. Narayanan,
E.P. Gusev,
P. Jamison,
B. Linder,
M. Steen,
K.K. Chan,
M. Frank, N. Bojarczuk,
M. Copel, [......],
A. Callegari,
M. Gribelyuk,
M.P. Chudzik,
C. Cabral Jr,
R. Carruthers,
C. D'Emic,
J. Newbury,
D. Lacey,
S. Guha,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: The flatband/threshold voltages (V<sub>fb</sub>/V<sub>t</sub>) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO<sub>2</sub> at poly-Si deposition temperatures is identified as the root cause for the poor V<sub>fb</sub>/V<sub>t</sub> control. No improvement in V<sub>t</sub> control is obtained by engineering physically closed Si<sub>3</sub>N<sub>4</sub> barrier layers on HfO<sub>2</sub>. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V<sub>fb</sub>/V<sub>t</sub> shifts are observed with HfO<sub>2</sub>. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al<sub>2</sub>O<sub>3</sub> cap layers on silicates.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
-
[show abstract]
[hide abstract]
ABSTRACT: Many of the proposed high permittivity gate dielectrics for silicon-based microelectronics rely on a stack configuration, with an SiO2 buffer layer to provide an interface. We describe a means for creating gate dielectrics with a direct yttrium silicate–silicon interface through the solid-state reaction of yttria and silicon oxynitride, avoiding the preparation of an oxide-free silicon surface. Characterization by medium-energy ion scattering indicates complete consumption of the underlying oxide through silicate formation during high-temperature annealing. Furthermore, the silicate dielectric exhibits small flat-band voltage shifts, indicating low quantities of charge, without passivation steps. Creation of a silicate–silicon interfaces by a simple route may enable the study of an alternate class of dielectrics. © 2002 American Institute of Physics.
Applied Physics Letters 11/2002; 81(22):4227-4229. · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: The stability of Al2O3 films during thermal processing will help determine their usefulness as an alternative gate dielectric for advanced complementary metal-oxide-semiconductor devices. We used medium energy ion scattering and atomic force microscopy to examine the degradation of ultrathin Al2O3 layers under ultrahigh vacuum annealing and the effects of low-temperature oxidation. No degradation is observed at 900 °C, but voids appear at higher temperatures. Growth of interfacial SiO2 takes place during low-pressure oxidation at 600 °C, which may limit the capacitance of extremely thin structures. © 2001 American Institute of Physics.
Applied Physics Letters 04/2001; 78(18):2670-2672. · 3.84 Impact Factor
-
E.P. Gusev,
D.A. Buchanan,
E. Cartier,
A. Kumar,
D. DiMaria,
S. Guha,
A. Callegari,
S. Zafar,
P.C. Jamison,
D.A. Neumayer, [......],
C. D'Emic,
P. Kozlowski,
K. Chan, N. Bojarczuk,
L.-A. Ragnarsson,
P. Ronsheim,
K. Rim,
R.J. Fleming,
A. Mocuta,
A. Ajmera
[show abstract]
[hide abstract]
ABSTRACT: Reviews recent progress in and outlines the issues for high-K
high-temperature (~1000°C) poly-Si CMOS processes and devices and
also demonstrate possible solutions. Specifically, we discuss device
characteristics such as gate leakage currents, flatband voltage shifts,
charge trapping, channel mobility, as well as integration and processing
aspects. Results on a variety of high-K candidates including HfO<sub>2
</sub>, Al<sub>2</sub>O<sub>3</sub>,
HfO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>, ZrO<sub>2</sub>, silicates,
and AlN<sub>y</sub>(O<sub>x</sub>) deposited on silicon by different
deposition techniques are shown to illustrate the complex issues for
high-K dielectric integration into current Si technology
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
-
D.A. Buchanan,
E.P. Gusev,
E. Cartier,
H. Okorn-Schmidt,
K. Rim,
M.A. Gribelyuk,
A. Mocuta,
A. Ajmera,
M. Copel,
S. Guha, N. Bojarczuk,
A. Callegari,
C. D'Emic,
P. Kozlowski,
K. Chan,
R.J. Fleming,
P.C. JAmison,
I. Brown,
R. Arndt
[show abstract]
[hide abstract]
ABSTRACT: This work demonstrates the integration of Al<sub>2</sub>O<sub>3
</sub> gate-dielectrics into a sub 0.1 μm n-MOS process using
polycrystalline silicon gates, Devices incorporating
Al<sub>2</sub>O<sub>3</sub> films with a dielectric constant ε-11
and electrical thickness t<sub>qm</sub><1.5 nm have been fabricated.
Gate leakage currents are ~100 times lower than those found in SiO<sub>2
</sub> films of equivalent thickness. Encouraging device characteristics
are shown. Charging due to slow states and/or fixed charge have been
shown to be in the 100 mV range which may be related to the somewhat
reduced mobility. The room temperature reliability of these devices
based upon the values of β (Weibull slope) and γ (voltage
acceleration) suggest that the Al<sub>2</sub>O<sub>3</sub> lifetime may
exceed that of SiO<sub>2</sub> films
Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
-
[show abstract]
[hide abstract]
ABSTRACT: We have used Raman spectroscopy to study indium nitride thin films grown by molecular beam epitaxy on (111) silicon substrates at temperatures between 450 and 550 C. The Raman spectra show well defined peaks at 443, 475, 491, and 591 cm{-1}, which correspond to the A_1(TO), E_1(TO), E_2^{high}, and A_1(LO) phonons of the wurtzite structure, respectively. In backscattering normal to the surface the A_1(TO) and E_1(TO) peaks are very weak, indicating that the films grow along the hexagonal c axis. The dependence of the peak width on growth temperature reveals that the optimum temperature is 500 C, for which the fullwidth of the E_2^{high} peak has the minimum value of 7 cm{-1}. This small value, comparable to previous results for InN films grown on sapphire, is evidence of the good crystallinity of the films. Comment: 3 pages, 1 eps figure, RevTeX
10/1999;
-
[show abstract]
[hide abstract]
ABSTRACT: Continued miniaturization of the different physical elements of a Si MOSFET required in order to attain higher transistor performance and greater economies of scale have spurred the need for significant materials innovations. This is most apparent in the search for the ideal high-k/Metal Gate stack that would replace conventional SiON/Poly-Si gate stacks. In this paper, we will review some of the recent advances and remaining challenges for high-k/Metal Gate stacks. It is shown that significant progress has been made towards improving electron mobility in HfO2/Metal Gate stacks by a combination of high temperature processes, nitrogen free interfaces and optimized metal deposition processes which result in mobility values competitive with SiON/Poly-Si. In addition by inserting nanoscale layers that comprise strongly electropositive gp. IIA and IIIB elements in between the HfO2and metal electrode stack have resulted in high mobility, band-edge aggressively scaled High-k/Metal Gate stacks. While much progress has been made with nMOSFET stacks, it will also be shown that a number of roadblocks remain with obtaining a similar solution for pMOSFET stacks, primarily due to the presence of thermally activated oxygen vacancies that induce large negative threshold voltage shifts towards midgap in HfO2/high workfunction metal stacks.
Microelectronic Engineering.
-
K.L. Lee,
M.M. Frank,
V. Paruchuri,
E. Cartier,
B. Linder, N. Bojarczuk,
X. Wang,
J. Rubino,
M. Steen,
P. Kozlowski, [......],
P. Flaitz,
M. Gribelyuk,
P. Jamison,
G. Singco,
V. Narayanan,
S. Zafar,
S. Guha,
P. Oldiges,
R. Jammy,
M. Ieong
[show abstract]
[hide abstract]
ABSTRACT: A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (V<sub>t</sub>) shifts in poly-Si/HfSiO devices and achieve good thickness scalability and gate stack stability. The new AlN cap layers provide better PFET V<sub>t</sub> control than, for example, Al<sub>2</sub>O<sub>3</sub> layers, and can be removed from NFETs without impacting device properties. We thus have achieved sub-100 nm device V<sub>t</sub> of 0.3-0.4 V with PFETs I<sub>on</sub> ~ 140 muA/mum at I<sub>off</sub> ~13 pA/mum, suitable for low-power technologies. Carrier mobilities are close to those of SiON control devices. Thus the V<sub>t</sub> problem impeding the implementation of poly-Si/high-k gate stacks for low power device applications has been resolved
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
