M. G. Pala

University of Grenoble, Grenoble, Rhône-Alpes, France

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Publications (92)162.1 Total impact

  • Marco G. Pala · Sylvan Brocard
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    ABSTRACT: This paper presents full-quantum 3-D simulations predicting the electrical performance of nanowire tunnel-FETs based on III–V hetero-junctions. Our calculations exploit an eight-band $mathrm {k}cdot mathrm {p}$ Hamiltonian within the nonequilibrium Green’s functions formalism and include phonon scattering. It is shown that the on-current of GaSb/InAs hetero-junction tunnel-FETs is limited by quantum confinement effects on the bandstructure induced by the small nanowire diameter necessary to preserve an optimal electrostatic integrity at short gate lengths. To circumvent this problem, additional on-current improvements with no substantial subthreshold swing degradation can be achieved by engineering the source region through the insertion of an InAs/GaSb/InAs quantum well along the transport direction. Such a design option is predicted to provide on/off-current ratios larger than $10^{7}$ even at $V_{DD}$ = 300 mV.
    IEEE Journal of the Electron Devices Society 05/2015; 3(3):1-1. DOI:10.1109/JEDS.2015.2395719
  • M. G. Pala · A. Cresti
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    ABSTRACT: We present a full-quantum approach to investigate self-heating effects in nanoelectronic devices and exploit it to simulate rough nanowire field-effect transistors. Self-heating is found to significantly contribute (up to about 16%) to the degradation of the transistor performances, with an impact that is stronger for stronger roughness. The mechanism at the origin of the enhanced backscattering is the temperature increase due to the thermal conductivity reduction and the consequent increase of electron-phonon coupling.
    Journal of Applied Physics 02/2015; 117(8):084313. DOI:10.1063/1.4913511 · 2.19 Impact Factor
  • Source
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    ABSTRACT: The disordered potential landscape in an InGaAs/InAlAs two-dimensional electron gas patterned into narrow wires is investigated by means of scanning gate microscopy. It is found that scanning a negatively charged tip above particular sites of the wires produces conductance oscillations that are periodic in the tip voltage. These oscillations take the shape of concentric circles whose number and diameter increase for more negative tip voltages until full depletion occurs in the probed region. These observations cannot be explained by charging events in material traps, but are consistent with Coulomb blockade in quantum dots forming when the potential fluctuations are raised locally at the Fermi level by the gating action of the tip. This interpretation is supported by simple electrostatic simulations in the case of a disorder potential induced by ionized dopants. This work represents a local investigation of the mechanisms responsible for the disorder-induced metal-to-insulator transition observed in macroscopic two-dimensional electron systems at low enough density.
    Physical Review B 02/2015; 91(7). DOI:10.1103/PhysRevB.91.075313 · 3.74 Impact Factor
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    ABSTRACT: This chapter summarizes the major challenges encountered in the fabrication, electrical characterization and quantum transport simulation of Silicon-based nanowires (SiNWs) intended for end of the road map logic complementary metal–oxide semiconductor (CMOS) devices. It illustrates the new solutions offered by NW technologies for nonvolatile memory (NVM) technologies both in terms of charge storage and resistive change types. Both top-down and bottom-up approaches are widely studied for the fabrication of NW metal-oxide-semiconductor field effect transistor (MOSFET) transistors. For the bottom-up approach, the vapor-liquidsolid (VLS) mechanism is the most commonly used route for making semiconductor NWs. The top-down approach combines lithographic steps and anisotropic etching processes or deposition to produce semiconductor NWs. This type of processing offers advantages compared to bottom-up synthesis techniques in terms of better yields, availability of mature technology and manufacturing techniques provided by the semiconductor industry for many years.
    Beyond-CMOS Nanodevices 2, 06/2014: pages 25-95; , ISBN: 9781848216556
  • Marco G. Pala · Alessandro Cresti
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    ABSTRACT: We present a quantum approach to simulate self-heating effects in transistors based on silicon nanowires and estimate the resulting performance degradation. Our self-consistent thermoelectric simulations are based on the nonequilibrium Green's function approach and provide the heat power transferred from electrons to phonons, thus allowing the calculation of the local temperature and its impact on the transistor output characteristics. We apply our approach to the simulation of a tri-gate transistor with a 14 nm channel length in the presence of surface roughness. Our results clearly indicate that self-heating effects are enhanced by surface roughness, with important consequences on the on-current of the device.
    2014 International Workshop on Computational Electronics (IWCE); 06/2014
  • M. G. Pala · D. Esseni
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    ABSTRACT: We present a numerical study based on a full quantum transport model to investigate the effects of interface traps in nanowire InAs Tunnel-FETs and MOSFETs by varying the trap energy level, its position and the working temperature. Our 3-D self-consistent simulations show that in Tunnel-FETs even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; shallow traps have the largest impact on subthreshold slope; and the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the Tunnel-FET characteristics. The impact of traps on the IV characteristics of MOSFETs is instead less dramatic, and the traps induced degradation of the subthreshold swing can be effectively contrasted by an aggressive oxide thickness scaling. Finally, we present a comparative analysis of the impact of interface traps on the performance variability of nanowire InAs Tunnel-FETs and MOSFETs by considering random distributions of traps.
    ECS Transactions 05/2014; 61(2):237-251. DOI:10.1149/06102.0237ecst
  • Sylvan Brocard · M.G. Pala · David Esseni
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    ABSTRACT: We propose to employ a grading of the molar fraction in the source region of III-V hetero-junction tunnel-FETs as a means to improve the on-current without degrading the subthreshold swing. Our full quantum simulations show that the molar-fraction grading increases the on-current by enlarging the hole wave function penetration from the source to the channel region. We also compare the performance of graded AlGaSb/InAs tunnel FETs and InAs MOSFETs and show that at $V_{rm DS}=0.3~{rm V}$, the tunnel device can outperform the MOSFET in terms of both on-current and subthreshold slope.
    IEEE Electron Device Letters 02/2014; 35(2):184-186. DOI:10.1109/LED.2013.2295884 · 3.02 Impact Factor
  • Source
    F. Martins · H. Sellier · M. G. Pala · B. Hackens · V. Bayot · S. Huant
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    ABSTRACT: Quantum rings patterned from two-dimensional semiconductor heterostructures exhibit a wealth of quantum transport phenomena at low temperature and in a magnetic field that can be mapped in real space thanks to dedicated scanning probe techniques. Here, we summarize our studies of GaInAs-based quantum rings by means of scanning gate microscopy both at low magnetic field, where Aharonov-Bohm interferences and the electronic local density of states are imaged, and at high magnetic field and very low temperatures, where the scanning probe can image Coulomb islands in the quantum Hall regime. This allows decrypting the apparent complexity of the magneto-resistance of a mesoscopic system in this regime. Beyond imaging and beyond a strict annular shape of the nanostructure, we show that this scanning-probe technique can also be used to unravel a new counter-intuitive behavior of branched-out rectangular quantum rings, which turns out to be a mesoscopic analog of the Braess paradox, previously known for road or other classical networks only.
    Physics of Quantum Rings, Edited by V.M. Fomin, 01/2014: chapter 5: pages 107-121; Springer., ISBN: 978-3-642-39197-2
  • Source
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    ABSTRACT: By combining quantum simulations of electron transport and scanning-gate microscopy, we have shown that the current transmitted through a semiconductor two-path rectangular network in the ballistic and coherent regimes of transport can be paradoxically degraded by adding a third path to the network. This is analogous to the Braess paradox occurring in classical networks. Simulations reported here enlighten the role played by congestion in the network.
    12/2013; DOI:10.1063/1.4848369
  • Source
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    ABSTRACT: Scanning gate microscopy is used to find the position of a quantum Hall island (QHI) which controls the electron transport through a mesoscopic quantum ring. Such QHIs emerging around potential inhomogeneities are tunnel-coupled with edge states. Approaching a polarized metallic tip over the QHIs gradually changes their surface and generates Coulomb blockade oscillations. This mechanism permits the identification of the center of the QHIs. Here, by sweeping the distance between the tip and the two dimensional electron gas, we clearly locate the center of an individual QHI.
    31st International Conference on the Physics of Semiconductors (ICPS); 12/2013
  • S. Brocard · M. G. Pala · D. Esseni
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    ABSTRACT: This work presents a systematic design study of nanowire Tunnel-FETs at LG=17nm employing a 3D Poisson-NEGF solver based on a 8×8 k·p Hamiltonian and including phonon scattering. In particular: (a) we revisit the design of GaSb-InAs based hetero-junction tunnel-FETs showing that this system is unlikely to yield a broken bangap profile at the very narrow features necessary for a good sub-VT slope value; (b) we propose new design options for hetero-junction tunnel-FETs, relying on the use of strain and of a graded molar fraction (xM) in AlxMGa(1-xM)Sb, which improve remarkably on current preserving optimal sub-VT slopes; (c) we show that interface defects can frustrate any design strategy aiming at sub-VT slope values below 60mV/dec.
    2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
  • David Esseni · M.G. Pala
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    ABSTRACT: This paper extends the analysis of the companion paper by presenting a comparative analysis of the impact of interface traps on the I-V characteristics of InAs nanowire tunnel FETs or MOSFETs with a spatially random distribution of traps. The physical mechanisms behind the effects of traps in either tunnel FETs or MOSFETs are compared and, furthermore, traps are also investigated as a possible source of device variability. Our results show that, in MOSFETs, an aggressive oxide thickness scaling can effectively counteract the degradation of the subthreshold slope (SS) possibly produced by interface traps. Tunnel FETs are instead more vulnerable to traps, which are probably the main hindrance to the experimental realization of tunnel FETs with an SS better than 60 mV/decade.
    IEEE Transactions on Electron Devices 09/2013; 60(9):2802-2807. DOI:10.1109/TED.2013.2274197 · 2.36 Impact Factor
  • M.G. Pala · David Esseni
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    ABSTRACT: This paper and the companion work present a full quantum study of the influence of interface traps on the I-V characteristics of InAs nanowire Tunnel-field effect transistors (FETs) and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on non equilibrium Green's function formalism, employing an 8 × 8 k·p Hamiltonian and accounting for phonon-scattering. In our model, traps can affect the I-V curves of the transistors both by modifying the device electrostatics and by directly participating the carrier transport. This paper investigates the impact of single trap on the I-V characteristics of Tunnel-FETs by varying the trap energy level, its volume and position, as well as the working temperature. Our 3-D self-consistent simulations show that: 1) even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; 2) shallow traps have the largest impact on subthreshold slopes; and 3) the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FETs I-V characteristics.
    IEEE Transactions on Electron Devices 09/2013; 60(9):2795-2801. DOI:10.1109/TED.2013.2274196 · 2.36 Impact Factor
  • Source
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    ABSTRACT: We explore transport across an ultra-small Quantum Hall Island (QHI) formed by closed quan- tum Hall edge states and connected to propagating edge channels through tunnel barriers. Scanning gate microscopy and scanning gate spectroscopy are used to first localize and then study a single QHI near a quantum point contact. The presence of Coulomb diamonds in the spectroscopy con- firms that Coulomb blockade governs transport across the QHI. Varying the microscope tip bias as well as current bias across the device, we uncover the QHI discrete energy spectrum arising from electronic confinement and we extract estimates of the gradient of the confining potential and of the edge state velocity.
    New Journal of Physics 05/2013; 15(1). DOI:10.1088/1367-2630/15/1/013049 · 3.67 Impact Factor
  • Semiconductor-On-Insulator materials, devices and circuits: physics, technology and diagnostics; 04/2013
  • Source
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    ABSTRACT: The unique properties of quantum hall devices arise from the ideal one-dimensional edge states that form in a two-dimensional electron system at high magnetic field. Tunnelling between edge states across a quantum point contact (QPC) has already revealed rich physics, like fractionally charged excitations, or chiral Luttinger liquid. Thanks to scanning gate microscopy, we show that a single QPC can turn into an interferometer for specific potential landscapes. Spectroscopy, magnetic field and temperature dependences of electron transport reveal a quantitatively consistent interferometric behavior of the studied QPC. To explain this unexpected behavior, we put forward a new model which relies on the presence of a quantum Hall island at the centre of the constriction as well as on different tunnelling paths surrounding the island, thereby creating a new type of interferometer. This work sets the ground for new device concepts based on coherent tunnelling.
    Scientific Reports 03/2013; 3:1416. DOI:10.1038/srep01416 · 5.58 Impact Factor
  • Chapter: Beyond CMOS
    Nanoscale CMOS: Innovative Materials, Modeling and Characterization, Edited by Francis Balestra, 03/2013: pages 443-470; Wiley and Sons., ISBN: 978-184821180-3
  • Source
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    ABSTRACT: We report on low temperature (100 mK) scanning gate experiments performed at high magnetic field (around 10 T) on a mesoscopic device patterned in an InGaAs/InAlAs heterostructure. Magnetotransport measurements yield signatures of ultra-small Quantum Hall Islands (QHI) formed by closed quantum Hall edge states and connected to propagating edge channels through tunnel barriers. Scanning gate microscopy and scanning gate spectroscopy are used to locate and probe a single QHI near a quantum point contact. The presence of Coulomb diamonds in the local spectroscopy confirms that Coulomb blockade governs transport across the QHI. Varying the microscope tip bias as well as current bias across the device, we uncover the QHI discrete energy spectrum arising from electronic confinement and we extract estimates of the gradient of the confining potential and of the edge state velocity.
  • Source
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    ABSTRACT: The Braess paradox, known for traffic and other classical networks, lies in the fact that adding a new route to a congested network in an attempt to relieve congestion can degrade counterintuitively the overall network performance. Recently, we have extended the concept of the Braess paradox to semiconductor mesoscopic networks, whose transport properties are governed by quantum physics. In this paper, we demonstrate theoretically that, alike in classical systems, congestion plays a key role in the occurrence of a Braess paradox in mesoscopic networks.
    Nanoscale Research Letters 08/2012; 7(1):472. DOI:10.1186/1556-276X-7-472 · 2.48 Impact Factor

Publication Stats

719 Citations
162.10 Total Impact Points

Institutions

  • 2015
    • University of Grenoble
      Grenoble, Rhône-Alpes, France
  • 2013
    • University of Leipzig
      • Institute of Theoretical Physics
      Leipzig, Saxony, Germany
  • 2009–2011
    • Grenoble Institute of Technology
      Grenoble, Rhône-Alpes, France
  • 2008
    • French National Centre for Scientific Research
      Lutetia Parisorum, Île-de-France, France
  • 2001–2007
    • Università di Pisa
      • Department of Information Engineering
      Pisa, Tuscany, Italy
  • 2005
    • Università Politecnica delle Marche
      • Department of Information Engineering (DII)
      Ancona, The Marches, Italy
  • 2004–2005
    • Università degli studi di Parma
      • Department of Information Engineering
      Parma, Emilia-Romagna, Italy
    • Università Degli Studi Roma Tre
      • Department of Mathematics and Physics
      Roma, Latium, Italy