J.P. Sage

Massachusetts Institute of Technology, Cambridge, Massachusetts, United States

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Publications (10)8.39 Total impact

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    ABSTRACT: This paper discusses on demonstration of charge-coupled devices in fully depleted SOI. CCDs implemented in FDSOI are expected to operate up to higher speeds than conventional bulk surface-channel CCDs. While FDSOI CCDs retain the high linearity and charge storage density of surface-channel CCDs, the buried oxide (BOX) layer allows strong fringing electric fields to penetrate beneath the gates and accelerate the transfer of charge from gate to gate. The simulation results illustrate the speed improvement with increasing BOX thickness. The improvement saturates when the BOX thickness becomes comparable to the gate length.
    SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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    ABSTRACT: We have designed and fabricated test structures that allow the determination of the critical current density and processing run-out of low T<sub>c</sub> Josephson junctions based only on room-temperature measurements. We demonstrated that the 300 K tunneling conductance of a junction barrier is proportional to the critical current at 4.2 K. This testing technique greatly reduced the time required to characterize a process wafer. In one demonstration we tested hundreds of devices across a 150-mm-diameter wafer in less than an hour. In another we used a selective niobium anodization process with only two mask levels to determine the critical current density of a Nb/AlO<sub>x</sub>/Nb trilayer within a day of its deposition. We have also used automated probing stations to decrease testing delays further and thus to improve process cycle time
    IEEE Transactions on Applied Superconductivity 07/1999; · 1.20 Impact Factor
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    J.P. Sage, D.A. Feld
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    ABSTRACT: A complete prototype superconductive programmable binary-analog matched filter for a 2-Gchip/s spread-spectrum modem has been operated for the first time and has performed correlation. We had previously demonstrated functionality of each individual element of the filter. The analog samplers had captured signals with bandwidths in the order of 10 GHz; the binary weighted taps, which utilize the unique quantum mechanical properties of superconductive circuits, had exhibited nondestructive readout as required; and the two digital shift registers, one that stores the binary code pattern and one that controls sampling of the input analog signal in the bank of track-hold cells, had functioned at 2 GHz. Now all of these elements have been operated together in low-frequency tests. A 7-bit (or “chip” in spread-spectrum terminology) pseudo-noise (pn) code sequence was loaded into the reference shift register in each of the seven possible positions while an analog version of the pn code with its amplitude varied over the full bipolar dynamic range of the filter was used as the incoming signal. The filter response peaked as expected when the analog signal and the binary reference were aligned. The peak and sidelobe responses agreed quantitatively with those predicted from calibration measurements made with uniform signals instead of pn codes
    IEEE Transactions on Applied Superconductivity 07/1999; · 1.20 Impact Factor
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    ABSTRACT: Digital circuits have been developed to interface superconductive electronic chips with high speed 50-Ω transmission lines. Digital data at 1 Gigabit per second was transferred through a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50-Ω transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interface circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50-Ω cable. In the second cryostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power-hungry semiconductor amplifiers
    IEEE Transactions on Applied Superconductivity 07/1999; · 1.20 Impact Factor
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    ABSTRACT: We have used a doubly planarized all-refractory technology for superconductive electronics (DPARTS) process to fabricate mixed-signal circuits that have more than 200 junctions per circuit and operate at 2 GHz. A 150-mm-diameter wafer can produce more than 400 chips, each 5 mm on an edge. The junctions had a critical current density of 1.7 kA/cm <sup>2</sup>. The wafers were evaluated at room temperature, both in- and post-process. In-process testing was used to detect parameter shifts during processing, while post-process testing used an automated testing station to test more than 3500 structures across each completed wafer and thus establish a large set of statistical data for studying the spread and targeting of parameter values. The circuits were fabricated in a class-10 clean room in which 0.25 μm CMOS and CCD devices were also produced. The DPARTS process could also be used for sub-μm fabrication, as it includes optical lithography with an i-line stepper; chemical-mechanical planarization at two levels; a self-aligned via process; and dry, anisotropic etching for all metal etching and via definition steps. The use of 150-mm-diameter wafers ensures that this process will be able to exploit technological advances in the standard silicon tool set as improvements become available. The results demonstrated here are a necessary precondition to yielding large volumes of superconductive electronic circuits containing devices with sub-μm dimensions
    IEEE Transactions on Applied Superconductivity 07/1999; · 1.20 Impact Factor
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    J.P. Sage, D.A. Feld
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    ABSTRACT: This paper describes the architecture and operation of a superconductive programmable matched filter that provides rapid synchronization information and data demodulation for a 2-GHz spread-spectrum modem. Results are reported for the first circuit fabrication runs using a new doubly planarized process. With the exception of circuits containing layout errors, all circuits have performed as intended and with characteristics that match well the predictions of JSIM simulations. The MVTL digital components and the buffer between the digital and analog circuits have been demonstrated for the first time. The seven-stage MVTL shift register in a complete prototype filter was operated at 1 GHz. In addition, combinations of (1) the MVTL digital shift register and the buffer and (2) the buffer and the T/H cell have been operated successfully, demonstrating that all of the components in the filter core will work together
    IEEE Transactions on Applied Superconductivity 07/1997; · 1.20 Impact Factor
  • J.P. Sage, D.A. Feld
    06/1997
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    K.Y. Tam, J.P. Sage
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    ABSTRACT: This paper describes the design and test of a high-speed monolithic track-and-hold circuit (T/H) consisting of a Josephson-junction-bridge current switch and a superconducting storage inductor. The bridge, under the control of a common-mode clock current, switches a balanced, differential input current. The T/H was fabricated using a 5-μm, 1000 A/cm<sup>2</sup> niobium trilayer process. Calculations and simulations of the T/H predict 5-bit dynamic range, 4.6-bit effective dc resolution, 750 MHz analog bandwidth, 725 ps acquisition time, 700 MS/s peak sampling rate, and an unlimited hold time. Measurements on the fabricated T/H verify the proper qualitative behavior of the T/H and show that it has 5-bit dynamic range, 4.5-bit effective dc resolution, 900 MHz analog bandwidth, and a 550 ps acquisition time, commensurate with a 900 MS/s sampling rate.
    IEEE Transactions on Applied Superconductivity 07/1995; · 1.20 Impact Factor
  • J.P. Sage, J.B. Green, A. Davidson
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    ABSTRACT: The authors describe the design, fabrication, and first successful operation in the gigahertz frequency range of a Josephson-junction-based sampling circuit designed to provide 6 b of resolution (~35 dB) and 10 GHz or more of bandwidth. The first experimental demonstration of a prototype circuit sampling a sine wave at up to 1 GHz is reported. This sampler has properties that make it amenable to incorporation into complex, mixed-analog/digital integrated circuits. Such a circuit can be used in the implementation of such signal processing subsystem components as a transient waveform data recorder, a programmable analog-binary correlator, and a flash analog-to-digital converter
    IEEE Transactions on Applied Superconductivity 04/1993; · 1.20 Impact Factor
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    ABSTRACT: Digital circuits have been developed to interface superconductive electronic chips with high speed 50- Ω Ω transmission lines. Digital data at 2 Gigabits per second was transferred from a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50- Ω Ω transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interf ace circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50- Ω Ω cable. In the second cyrostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power - hungry semiconductor amplifiers.