F. Pescador

Universidad Politécnica de Madrid, Madrid, Madrid, Spain

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Publications (39)9.98 Total impact

  • J. Wei, R. Ren, E. Juarez, F. Pescador
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    ABSTRACT: This paper provides a concrete implementation and comprehensive assessment of the energy-based fair queuing (EFQ) scheduling algorithm based on the Linux operating system. EFQ is an extended application of the classical fair queuing algorithm in the energy domain. It is designed to provide proportional power sharing as well as effective time-constraint compliance in energy-centric power management (PM) schemes, a type of operating system-level PM schemes that are targeted at providing a battery lifetime guarantee for energy-limited mobile systems. In this paper work, the structure of the Linux completely fair scheduler (CFS) has been effectively utilized to ease the EFQ implementation and reduce the scheduling overhead. Around 150 lines of code have been added to the Linux kernel V3.3 to achieve the EFQ-related functions and to implement the system calls that are required by the Linux user space. To assess the properties of the EFQ scheduler, a test-bench based on the POSIX threads has been developed and the benchmarks of an open-source embedded suite are referred to program the threads under test. The EFQ algorithm is assessed from two aspects, energy management and real-time scheduling. Experimental results on energy management show that EFQ is more effective than the CFS scheduler in managing energy and it can achieve a proportional share of the system power regardless of on which device the energy is spent. Experimental results on real-time scheduling demonstrate that EFQ can achieve strict time-constraint compliance and a robust response time upon the increase of energy estimation error and active tasks.
    IEEE Transactions on Consumer Electronics 01/2014; 60(2):267-275. · 1.09 Impact Factor
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    ABSTRACT: High Efficiency Video Coding (HEVC) is a new video coding standard created by the JCT-VC group within ISO/IEC and ITU-T. HEVC is targeted to provide the same quality as H.264 at about half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. Up to now, only a few decoder implementations have been reported, most of them oriented to carry out a complexity analysis. In this paper, a DSP-based implementation of the HEVC HM9.0 decoder is presented. Up to the best of our knowledge, it is the first DSP-based implementation shown in the scientific literature. Several tests have been carried out to measure the decoder performance and the computational load distribution among its functional blocks. These results have been compared with the ones obtained with the decoder implementations reported up to date. Finally, based on the results obtained in previous works regarding software optimization of DSP-based decoders, realtime could be achieved for SD formats with a single DSP after optimizing our HEVC decoder. For HD formats, multi-DSP technology will be needed.
    IEEE Transactions on Consumer Electronics 01/2013; 59(2):391-399. · 1.09 Impact Factor
  • J. Wei, E. Juarez, M.J. Garrido, F. Pescador
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    ABSTRACT: This paper extends the traditional fair queuing scheduling to the energy management domain, and presents the energy-based fair queuing scheduling, a novel class of energy-aware scheduling algorithms that support proportional energy use, effective time-constraint meeting and a flexible trade-off between them. The proposed algorithm, in combination with a mechanism that restricts the battery discharge rate, can achieve a target lifetime for Operating System (OS)-based mobile devices by including total energy consumption on all system components and systematically managing energy as the first-class resource.
    Consumer Electronics (ICCE), 2013 IEEE International Conference on; 01/2013
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    ABSTRACT: In this paper, an energy estimation methodology based on performance monitor counters (PMC) is proposed to estimate the energy consumption of RVC-CAL video codec specifications. The proposed PMC-driven methodology is able to automatically identify the most appropriate events and training data to cover the main application characteristics. In addition, knowledge of the hardware platform employed is not required. Therefore, this methodology can be easily implemented on other PMC-available systems while keeping the estimation accuracy. It is worth noting that this is an attractive asset to analyze the energy consumption of RVC-CAL codec specifications. Besides, the methodology reduces the PMC redundancy and, thus, the overhead introduced when applied to on-line power management. Experimenting on two RVC-CAL decoders, H.264 and MPEG4 Part2 SP, a coarse estimation model based on instructions per cycle (IPC) and the proposed PMC-driven model are compared. The results show that the PMC-driven model can achieve for the H.264 and MPEG4 Part2 SP decoders average estimation errors of 5.95% and 5.01%, respectively, in comparison to the 17.11% and 13.65% average errors obtained with the IPC-based model. As a consequence, this methodology is suggested to be combined into the RVC framework to help the designer to have an overview of the energy consumption of the specification actors at earlier design stages.
    Signal Processing Image Communication 01/2013; 28(10):1303–1314. · 1.29 Impact Factor
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    ABSTRACT: During the last decades, new video compression standards arose every few years with always higher compression gains and considerable increases on the computational cost. Single core processors have reached their limit and multicore processors are there to overcome this issue to give more processing power. In order to accelerate the implementation of new video coding standards, MPEG has standardized an alternative framework to describe video decoders. It is based on reference decoders written in the RVC CAL dataflow actor language. From these descriptions, a compiler - Open RVC CAL compiler (Orcc) - allows the automatic generation of C code dedicated to the target processor. In this paper, a DSP based decoder compliant with the new High Efficiency Video Coding (HEVC) standard has been implemented using a CAL RVC model as a starting point. This is the first implementation of an HEVC decoder with DSP technology based on a HEVC RVC CAL model. The decoder has been compared in performance with a GPP implementation, also based on the RVC CAL model, and outperforms it by more than 50%. Additionally, the performance of this decoder is compared with that of other DSP-based HEVC decoders implemented without using the Orcc infrastructure1.
    IEEE Transactions on Consumer Electronics 01/2013; 59(4):839-847. · 1.09 Impact Factor
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    ABSTRACT: In this paper, the implementation of a Multi-DSP based video decoder compliant with the H.264/SVC standard (14496-10 Annex G) is presented. An optimized single DSP-based decoder implementation has been splitted in two processes: the frame decoding (entropy decoding and motion compensation) and the deblocking filter. A multi-DSP device has been used to parallelize the execution of the processes. The performance has been measured using H.264/SVC sequences with different configurations.
    Consumer Electronics (ISCE), 2013 IEEE 17th International Symposium on; 01/2013
  • F. Pescador, M.J. Garrido, E. Juarez, C. Sanz
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    ABSTRACT: High Efficiency Video Coder (HEVC) will become a new MPEG International Standard by the end of 2012. HEVC is targeted to provide the same quality as H.264 at about a half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. In this paper, a preliminary implementation of an HEVC video decoder based on a DSP is presented and compared with a formerly developed H.264 DSP-based decoder.
    Consumer Electronics (ICCE), 2013 IEEE International Conference on; 01/2013
  • J. Wei, E. Juarez, M.J. Garrido, F. Pescador
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    ABSTRACT: Currently, the usefulness of many mobile systems is largely limited by the battery lifetime. In this paper, energy-based fair queuing (EFQ) is proposed as a pivotal instrument to maximize the user experience in this type of system. Energy-based fair queuing is a novel class of energy-aware scheduling algorithms that support proportional energy use, effective time-constraint compliance and a flexible trade-off between them. The combination of EFQ with lifetime-oriented power management schemes opens the door to maximize the user experience of battery-limited mobile systems. Moreover, it is suggested to merge traditional energy-efficient algorithms with EFQ to further improve the user experience. The proposed EFQ algorithm is implemented in the Linux kernel V3.3 and verified on a testbench based on an open source Linux scheduler simulator with user-specified energy loads. Simulation results show that EFQ is more effective and flexible than the Linux scheduler in maximizing the user experience of energy-limited mobile systems.
    IEEE Transactions on Consumer Electronics 01/2013; 59(3):690-698. · 1.09 Impact Factor
  • EDULEARN12 Proceedings. 01/2012;
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    ABSTRACT: An implementation of a real-time 3D videoconferencing system using the currently available technology is presented. This approach is based on the side by side spatial compression of the stereoscopic images. The encoder and the decoder have been implemented in a standard personal computer and a conventional 3D compatible TV has been used to present the frames. Moreover, the users without 3D technology can use the system because 2D compatibility mode has been implemented in the decoder. The performance results show that a conventional computer can be used for encoding/decoding audio and video streams and the delay in the transmission is lower than 200 ms.
    01/2012;
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    ABSTRACT: In this paper, a H.264/SVC compliant video client based on a SoC is presented. The SoC includes two processors, a General Purpose Processor to execute a Linux-based operating system and a Digital Signal Processor optimized to decode video sequences. The computational load of the application has been distributed between both processors. The performance results demonstrate that the developed system is able to decode six-layer scalable sequences in real-time.
    Consumer Electronics (ISCE), 2012 IEEE 16th International Symposium on; 01/2012
  • J. Wei, E. Juarez, F. Pescador, M.J. Garrido
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    ABSTRACT: In this paper we introduce the Starting-Energy Fair Queuing (SEFQ), a novel class of energy-aware scheduling algorithms aim to guarantee a target lifetime to mobile devices while providing proportional energy consumption and time-constraint meeting to tasks. With the extension of fair queuing to the energy domain, energy consumption of CPU is managed in a way that each task is guaranteed a share of the average power of a fixed period. The simulation results show that the performance of time-sensitive tasks can be traded-off with their fairness.
    Consumer Electronics (ISCE), 2012 IEEE 16th International Symposium on; 01/2012
  • R. Ren, E. Juarez, F. Pescador, C. Sanz
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    ABSTRACT: In this paper, a methodology which aims to solve the accuracy susceptibility problem in PMC-driven energy estimation models is developed. The application characteristics representativeness of PMCs and training benchmarks to generate an accurate and stable energy estimation model are considered. The results show a good accuracy and stability with average relative error of 4.8%.
    Consumer Electronics (ISCE), 2012 IEEE 16th International Symposium on; 01/2012
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    ABSTRACT: In this paper, a performance comparison of two H.264/SVC-compliant video decoders, Joint Scalable Video Model and Open SVC Decoder, is presented. The performance, in terms of time spent to decode a stream, has been compared in PC and Digital Signal Processor (DSP) environments. The performance of the Open SVC Decoder running on the PC is between three and eight times better than achieved with the JSVM decoder; while in the DSP environment, the improvement is between five and twelve times. These results show that the Open SVC Decoder is more suitable as starting point for the implementation of embedded applications based on DSP.
    Consumer Electronics (ISCE), 2011 IEEE 15th International Symposium on; 07/2011
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    ABSTRACT: In this paper, the implementation of a DSP based video decoder compliant with the H.264/SVC standard (14496-10 Annex G) is presented. A PC-based decoder implementation has been ported to a commercial DSP. Performance optimizations have been carried out improving the initial version performance about 32% and reaching real time for CIF sequences. Moreover, conformance tests have been done using different H.264/SVC streams. This decoder will be the core of a multimedia terminal that will trade off energy against quality of experience.
    Consumer Electronics (ICCE), 2011 IEEE International Conference on; 02/2011
  • F. Pescador, E. Juarez, M. Raulet, C. Sanz
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    ABSTRACT: In this paper, the implementation of a DSP-based video decoder compliant with the H.264/SVC standard (14496-10 Annex G) is presented. A PC-based decoder implementation has been ported to a commercial DSP. Performance optimizations have been carried out improving the initial version performance about 40% and reaching real time for CIF sequences. Moreover, the performance has been characterized using H.264/SVC sequences with different kinds of scalabilities and different bitrates. This decoder will be the core of a multimedia terminal that will trade off energy against quality of experience 1 .
    IEEE Transactions on Consumer Electronics 01/2011; 57(2):705-712. · 1.09 Impact Factor
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    ABSTRACT: DVB-H is a mobile TV broadcasting system that is being deployed in many countries around the world. Although specific terminals do exist, it is not very common for mobile terminals (e.g. smartphones or tablets) to be DVB-H enabled. Therefore, it might be desirable to have some kind of device that could retransmit the DVB-H services using a more established system such as WiFi. A prototype system, based on FPGA and DSP, that is able to receive a DVB-H multiplex, extract a desired service and retransmit it to any wired or wireless Ethernet-type network is presented. It can also decode and present the selected program 1 .
    IEEE Transactions on Consumer Electronics 01/2011; 57(2):372-378. · 1.09 Impact Factor
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    ICERI2011 Proceedings. 01/2011;
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    ABSTRACT: In this paper, the implementation of a DSP-based for DVB-H is presented. The gateway allows to extract a program (audio and video) included in a DVB-H compliant stream and transmit it in RTP/UDP packets through an Ethernet network. Moreover, to supervise the system operation, the audio and video streams of the selected program are decoded and presented in an LCD monitor. Real time performance has been achieved using about 20% of CPU for retransmit and decode one video service.
    01/2011;
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    ABSTRACT: In this paper, a implementation of a DSP-based IP set-top box (IP-STB) to decode CIF sequences compliant with the new Scalable Video Coding standard (14496-10 Amd 3) using Open SVC Decoder (OSD) is presented. The OSD software, designed for the PC environment, has been integrated into a previously developed IP-STB prototype. About 15 CIF frames per second can be decoded with the IP-STB.
    Consumer Electronics (ISCE), 2010 IEEE 14th International Symposium on; 07/2010