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J. Alvarez-Muñiz,
E. Amaral Soares,
A. Berlin, M. Bogdan,
M. Boháčová,
C. Bonifazi,
W. R. Carvalho Jr,
J. R. T. de Mello Neto,
P. Facal San Luis,
J. F. Genat, [......],
M. Monasor,
P. Privitera,
A. Ramos de Castro,
L. C. Reyes,
B. Rouille d'Orfeuil,
E. M. Santos,
S. Wayne,
C. Williams,
E. Zas,
J. Zhou
[show abstract]
[hide abstract]
ABSTRACT: We present the design, implementation and data taking performance of the
MIcrowave Detection of Air Showers (MIDAS) experiment, a large field of view
imaging telescope designed to detect microwave radiation from extensive air
showers induced by ultra-high energy cosmic rays. This novel technique may
bring a tenfold increase in detector duty cycle when compared to the standard
fluorescence technique based on detection of ultraviolet photons. The MIDAS
telescope consists of a 4.5 m diameter dish with a 53-pixel receiver camera,
instrumented with feed horns operating in the commercial extended C-Band (3.4
-- 4.2 GHz). A self-trigger capability is implemented in the digital
electronics. The main objectives of this first prototype of the MIDAS telescope
- to validate the telescope design, and to demonstrate a large detector duty
cycle - were successfully accomplished in a dedicated data taking run at the
University of Chicago campus prior to installation at the Pierre Auger
Observatory.
08/2012;
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J. Alvarez-Muñiz,
A. Berlin, M. Bogdan,
M. Boháčová,
C. Bonifazi,
W. R. Carvalho Jr,
J. R. T. de Mello Neto,
P. Facal San Luis,
J. F. Genat,
N. Hollon,
E. Mills,
M. Monasor,
P. Privitera,
L. C. Reyes,
B. Rouille d'Orfeuil,
E. M. Santos,
S. Wayne,
C. Williams,
E. Zas,
J. Zhou
[show abstract]
[hide abstract]
ABSTRACT: We present a search for microwave emission from air showers induced by
ultrahigh energy cosmic rays with the microwave detection of air showers
experiment. No events were found, ruling out a wide range of power flux and
coherence of the putative emission, including those suggested by recent
laboratory measurements.
05/2012;
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A Andreani,
A Annovi,
M Beretta, M Bogdan,
M Citterio,
F Alberti,
P Giannetti,
A Lanza,
D Magalotti,
M Piendibene,
others
Journal of Instrumentation. 01/2012; 7(08):C08007.
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A Andreani,
A Andreazza,
A Annovi,
M Beretta,
V Bevacqua, M Bogdan,
E Bossini,
A Boveia,
F Canelli,
Y Cheng, [......],
A Todri,
R Tripiccione,
J Tuggle,
V Vercesi,
M Villa,
R A Vitullo,
G Volpi,
J Wu,
K Yorita,
J Zhang
[show abstract]
[hide abstract]
ABSTRACT: The existing three-level ATLAS trigger system is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to ~ 200 Hz for permanent storage at the LHC design luminosity of 1034 cm−2 s−1. When the LHC exceeds the design luminosity, the load on the Level-2 trigger system will significantly increase due both to the need for more sophisticated algorithms to suppress background and the larger event sizes. The Fast Tracker is a proposed upgrade to the current ATLAS trigger system that will operate at the full Level-1 accepted rate of 100 kHz and provide high quality tracks at the beginning of processing in the Level-2 trigger, by performing track reconstruction in hardware with massive parallelism of associative memories. The concept design is being advanced and justified with the performance in important physics areas, b-tagging, τ-tagging and lepton isolation. The prototyping with current technology is underway and R&D with new technologies has been started.
Journal of Instrumentation 12/2010; 5(12):C12037. · 1.87 Impact Factor
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A. Andreani,
A. Andreazza,
A. Annovi,
M. Beretta,
V. Bevacqua, M. Bogdan,
E. Bossini,
A. Boveia,
F. Canelli,
Y. Cheng, [......],
A. Todri,
R. Tripiccione,
J. Tuggle,
V. Vercesi,
M. Villa,
R.A. Vitullo,
G. Volpi,
J. Wu,
K. Yorita,
J. Zhang
[show abstract]
[hide abstract]
ABSTRACT: As the LHC luminosity is ramped up to 3×10<sup>34</sup> cm<sup>-2</sup> s<sup>-1</sup> and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested in, and at the same time suppress the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK) is a proposed upgrade to the current ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK solves the combinatorial challenge inherent to tracking by exploiting massive parallelism of associative memories that can compare inner detector hits to millions of pre-calculated patterns simultaneously. The tracking problem within matched patterns is further simplified by using pre-computed linearized fitting constants and leveraging fast DSPs in modern commercial FPGAs. Overall, FTK is able to compute the helix parameters for all tracks in an event and apply quality cuts in less than 100 μs. The system design is defined and studied with respect to high transverse momentum (high-P<sub>T</sub>) Level-2 objects: b-jets, tau-jets, and isolated leptons. We test FTK algorithms using ATLAS full simulation with WH events up to 3×10<sup>34</sup> cm<sup>-2</sup> s<sup>-1</sup> luminosity and comparing FTK results with the offline tracking capability. We present the architecture and the reconstruction performances for the mentioned high-P<sub>T</sub> Level-2 objects.
Real Time Conference (RT), 2010 17th IEEE-NPSS; 06/2010
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K. Anikeev, M. Bogdan,
R. Demaat,
W. Fedorko,
H. Frisch,
K. Hahn,
M. Hakala,
P. Keener,
Y. Kim,
J. Kroll, [......],
S. Pitkanen,
B. Reisert,
V. Rusu,
H. Sanders,
M. Shochet,
H. Stabenau,
R. Van Berg,
P. Wilson,
D. Whiteson,
P. Wittich
[show abstract]
[hide abstract]
ABSTRACT: We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.
IEEE Transactions on Nuclear Science 05/2006; · 1.45 Impact Factor
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J. Adelman,
A. Annovi,
M. Aoki,
A. Bardi,
F. Bedeschi,
S. Beiforte,
J. Bellinger,
E. Berry,
M. Bitossi, M. Bogdan, [......],
B. Simoni,
F. Spinella,
P. Squillacioti,
F. Tang,
S. Torre,
R. Tripiccione,
G. Volpi,
U.K. Yang,
L. Zanello,
A.L. Zanetti
[show abstract]
[hide abstract]
ABSTRACT: The silicon vertex trigger (SVT) in the CDF experiment at Fermilab performs fast and precise track finding and fitting at the second trigger level and has been a crucial element in data acquisition for Run II physics. However as luminosity rises, multiple interactions increase the complexity of events and thus the SVT processing time, reducing the amount of data CDF can record. The SVT upgrade aims to increase the SVT processing power to restore at high luminosity the original CDF DAQ capability. We describe the first steps in the SVT upgrade, consisting of a new associative memory with 4 times the number of patterns, and a new track fitter to take advantage of these patterns. We describe the system, its tests and its performance
Nuclear Science Symposium Conference Record, 2005 IEEE; 11/2005
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[show abstract]
[hide abstract]
ABSTRACT: We present the data acquisition system for Phase I of the Q/U Imaging ExperimenT (QUIET) that will operate arrays of 91 4-channel W-band (90 GHz) and 19 4-channel Q-band (40 GHz) receivers, both placed on 1.4 m and 7 m telescopes, in Chajnantor, Chile. The analog signals from the receivers, modulated at 4 kHz, are read out by up to 13 custom-made 6U VME modules implemented each with 32 18-bit, SAR ADCs. The sampling for all 364 (or 76) channels is simultaneous on one 800 kHz, low jitter clock for each array. Data are then processed locally with field programmable gate arrays (FPGAs) that perform signal demodulation and averaging over 10 ms, while blanking out the transition edges of the 4 kHz switching frequency, during which the receivers outputs are not well defined. The calculated values are continuously read out through the VME backplane to the crate controller and then passed, along with the absolute time stamp and telescope pointing information, to a remote PC for storage. One of the ADC modules in the system acts as "master", generating the sampling clock as well as the switching and data processing synchronization signals for the whole array. In the future, the DAQ will be upgraded to accommodate the requirements of Phase II of the QUIET experiment with arrays containing up to 1,000 receivers. The full design and multi-card test results will be described.
Nuclear Science Symposium Conference Record, 2005 IEEE; 11/2005
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[show abstract]
[hide abstract]
ABSTRACT: We describe a FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the central outer tracker (COT) in the CDF experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC, which is implemented as a 9U VME card, has been built around two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHZ LVDS inputs, multiple phase locked clock modules, and abundant memory. The TDC system would operate with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each wire input can accept up to 7 hits per collision. Memory pipelines are included for each channel to allow deadtimeless operation in the first-level trigger; the pipeline has a depth of 5.5 μs to allow the data to pass into one of four separate level-two buffers for readout. If the level-two buffer is accepted, the data are passed through a processor implemented in the FPGA to encode the relative time-to-digital values by using the memory positions and addresses of the transitions due to the input pulses. This processing and moving of the data takes 12 microseconds; the results are then loaded into an output VME memory. A separate memory contains the resulting word count, which is used in performing a VME 64-bit chain block transfer of an entire sixteen-card crate. The TDC must also produce prompt trigger flags for a tracking trigger processor called the extremely fast tracker (XFT). This separate path uses the same input data but passes the stream through a special processor, also implemented in the FPGA, to develop the trigger data delivered with a 22 ns clock to the XFT through a high-speed transmission cable assembly. The full TDC design and multi-card test results will be described.
Nuclear Science Symposium Conference Record, 2004 IEEE; 11/2004
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M. Bogdan,
R. Demaat,
W. Fedorko,
H. Frisch,
K. Hahn,
M. Hakala,
P. Keener,
Y. Kim,
J. Kroll,
S. Kwang, [......],
C. Neu,
M. Pitkanen,
B. Reisert,
V. Rusu,
H. Sanders,
S.H. Stabenau,
R. Van Berg,
P. Wilson,
D. Whiteson,
P. Wittich
[show abstract]
[hide abstract]
ABSTRACT: The CDF data acquisition and trigger system is being upgraded to significantly increase the bandwidth for the upcoming high luminosity running of the Tevatron Collider (run IIb). This paper focuses on the upgrade for the level 2 (L2) trigger decision crate. This crate is at the heart of the L2 trigger system and has to interface with many different subsystems both upstream and downstream. The challenge of this upgrade is to have a uniform design to be able to interface with many different data paths upstream, merge and process the data at high speed for fast L2 trigger decision making, and minimize the impact on the running CDF experiment during the commissioning phase. In order to meet this challenge, the design philosophy of the upgrade is to use one type of general purpose motherboard, with a few powerful modern FPGAs and SRAMs, to interface any user data with any industrial standard link through the use of mezzanine cards. This general purpose motherboard, named "Pulsar" (PULSer And Recorder), is fully self-testable at board level as well as at system level. CERN S-LINK is chosen to allow Pulsar to communicate with commodity processors via high bandwidth, low latency S-LINK-to-PCI cards. Knowledge gained by using S-LINK at CDF will be transferable to and from the LHC community.
Nuclear Science Symposium Conference Record, 2004 IEEE; 11/2004
-
W. Ashmanskas,
A. Barchiesi,
A. Bardi,
M. Bari,
M. Baumgart,
S. Belforte,
A. Belloni,
J. Berryhill, M. Bogdan,
R. Carosi, [......],
H. Sanders,
S. Sarkar,
A. Sernenov,
M. Shochet,
T. Speer,
F. Spinella,
X. Wu,
U. Yang,
L. Zanello,
A.M. Zanetti
[show abstract]
[hide abstract]
ABSTRACT: The online silicon vertex tracker (SVT) is the new trigger processor dedicated to the two-dimensional (2-D) reconstruction of charged particle trajectories at the Level 2 of the Collider Detector at Fermilab (CDF) trigger. The SVT links the digitized pulse heights found within the silicon vertex detector to the tracks reconstructed in the central outer tracker by the Level 1 fast-track finder. Preliminary tests of the system took place during the October 2000 commissioning run of the Tevatron Collider. During the April-October 2001 data taking, it was possible to evaluate the performance of the system. In this paper, we review the tracking algorithms implemented in the SVT and we report on the performance achieved during the early phase of run II.
IEEE Transactions on Nuclear Science 07/2002; · 1.45 Impact Factor
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A. Bardi,
A Belloni,
R Carosi,
A Cerri,
G Chlachidze,
M. Dell'Orso,
S Donati,
S. Galeotti,
P Giannetti,
V Glagolev, [......],
R Culbertson,
H. Frisch,
T Nakaya,
H. Sanders,
M Shochet,
U. Yang,
Y Liu,
L Moneta,
T Speer,
X Wu
[show abstract]
[hide abstract]
ABSTRACT: The Online Silicon Vertex Tracker is the new CDF-II level 2 trigger processor designed to reconstruct 2-D tracks within the Silicon Vertex Detector with high speed and accuracy. By performing a precise measurement of impact parameters the SVT allows tagging online B events which typically show displaced secondary vertices. Physics simulations show that this will greatly enhance the CDF-II B-physics capability. The SVT has been fully assembled and operational since the beginning of Tevatron RunII in April 2001. In this paper we briefly review the SVT design and physics motivation and then describe its performance during the early phase (April-October 2001) of run II. Comment: Invited talk at the ICALEPCS2001 Conference, Novermber 27-30, 2001, San Jose, California, 5 pages, LaTex, 3 figures
12/2001;
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A Bardi,
A Belloni,
R Carosi,
G Chlachidze,
M Dell 'orso,
S Donati,
S Galeotti,
P Giannetti,
V Glagolev,
E Meschi, [......],
H Frisch,
T Nakaya,
H Sanders,
M Shochet,
U Yang,
A Cerri,
Y Liu,
L Moneta,
T Speer,
X Wu
[show abstract]
[hide abstract]
ABSTRACT: The Silicon Vertex Tracker (SVT) is the new trigger processor which reconstructs 2-D tracks with high speed and accuracy at the level 2 trigger of the CDFII exper-iment. SVT allows tagging events with secondary vertices and therefore enhances the CDFII B-physics capability. SVT has been fully assembled and operational since the beginning of Tevatron RunII in April 2001. In this paper we brieey re-view the SVT design and physics motivation and then describe its performance during the early phase of CDF RunII.
7th International Conference on Advanced Technology and Particle Physics (ICATPP 2001), Villa Olmo, Como Italy; 10/2001
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W Ashmanskas,
A Bardi,
M Bari,
S Belforte,
J Berryhill, M Bogdan,
A Cerri,
A.G Clark,
G Chlachidze,
R Condorelli, [......],
L Ristori,
H Sanders,
A Semenov,
G Signorelli,
M Shochet,
T Speer,
F Spinella,
P Wilson,
X Wu,
A Zanetti
[show abstract]
[hide abstract]
ABSTRACT: Real time pattern recognition is becoming a key issue in many position sensitive detector applications. The CDF collaboration is building SVT: a specialized electronic device designed to perform real time track reconstruction using the Silicon VerteX detector (SVX II). This will strongly improve the CDF capability of triggering on events containing b quarks, usually characterized by the presence of a secondary vertex.SVT is designed to reconstruct in real time charged particles trajectories using data coming from the silicon vertex detector and the central outer tracker drift chamber. The SVT architecture and algorithm have been specially tuned to minimize processing time without degrading parameter resolution.
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment. 10/1999;
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Il Nuovo Cimento,
A. Bardi,
M. Bari,
S Belforte, M. Bogdan,
A Cerri,
G Chlachidze,
R. Condorelli,
R Culbertson,
S. Galeotti,
A. Leger Meschi,
F. Morsani,
Ers Semenov
[show abstract]
[hide abstract]
ABSTRACT: ) University of Chicago, USA ( 2 ) University and Scuola Normale Superiore and INFN Pisa, Italy ( 3 ) INFN Trieste, Italy ( 4 ) University of Geneve, Switzerland ( 5 ) Joint Institute for Nuclear Research, Dubna, Russia Summary. --- The Silicon Vertex Tracker is the CDF online tracker which will reconstruct 2D tracks using hit positions measured by the Silicon Vertex Detector and Central Outer Chamber tracks found by the eXtremely Fast Tracker. The precision measurement of the track impact parameter will allow triggering on events containing B hadrons. This will allow the investigation of several important problems in B physics, like CP violation and Bs mixing, and to search for new heavy particles decaying to bb. 1. -- Introduction The precision measurement of track i
09/1999;
-
W Ashmanskas,
A. Bardi,
M. Bari,
S Belforte,
J. Berryhill, M. Bogdan,
A Cerri,
G Chlachidze,
R. Condorelli,
R Culbertson, [......],
F. Morsani,
T Nakaya,
G Punzi,
L Ristori,
A Semenov,
G Signorelli,
M Shochet,
T Speer,
F Spinella,
X Wu
[show abstract]
[hide abstract]
ABSTRACT: dy of CP violation in the b sector (i.e. in the B 0 d ! + Gamma decay) and of B 0 s mixing. We discuss the overall architecture, algorithms and hardware implementation of the system. 1. Introduction The Tevatron pp Collider and the CDF detector are presently being upgraded for Run II operation (to begin in the year 2000). The Tevatron centerof -mass energy will be increased from 1.8 TeV to 2.0 TeV and the instantaneous luminosity by almost one order of magnitude, to reach 1-2Theta10 32 cm Gamma2 sec Gamma2 , with the goal to take 2 fb Gamma1 of data [1]. The bunch spacing will be reduced from 3.7 s to 132 ns. To cope with the higher rate of interaction, all the Data Acquisition will be fully replaced with faster devices.
06/1999;
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W. Ashmanskas,
A. Bardi,
M. Bari,
S. Belforte,
J. Berryhill, M. Bogdan,
A. Cerri,
A. G. Clark,
G. Chlachidze,
R. Condorelli, [......],
L. Ristori,
H. Sanders,
A. Semenov,
G. Signorelli,
M. Shochet,
T. Speer,
F. Spinella,
P. Wilson,
X. Wu,
A. M. Zanetti
[show abstract]
[hide abstract]
ABSTRACT: The Silicon Vertex Tracker is the CDF online tracker which will reconstruct 2D tracks using hit positions measured by the
Silicon Vertex Detector and Central Outer Chamber tracks found by the extremely Fast Tracker. The precision measurement of
the track impact parameter will allow triggering on events containing B hadrons. This will allow the investigation of several
important problems in B physics, like CP violation and Bs mixing, and to search for new heavy particles deca ying to bb.
PACS 07.05.HdData acquisition: hardware and software
PACS 29.40.GxTracking and position-sensitive detectors
PACS 01.30.CcConference Proceedings
Il Nuovo Cimento A 04/1999; 112(11):1239-1243.
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[show abstract]
[hide abstract]
ABSTRACT: A dual method of configuring programmable logic devices from the
Altera FLEX 10K family is presented. A passive serial configuration is
employed with the programming object files transferred from an onboard
EPROM. The second source, selectable with a switch, is an external PC
via a BitBlaster connection. Presently, Altera has no recommendation for
a switchable source of programming files. The scheme presented has been
tested on several configurations of single and multiple daisy-chained
devices. This method enables field programmability together with EPROM
power-up configuration for 10K devices. It proved to be a valuable tool
during the debugging stage
Real Time Conference, 1999. Santa Fe 1999. 11th IEEE NPSS; 02/1999
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D. Sigg,
A. Badertscher, M. Bogdan,
P. F. A. Goudsmit,
H. J. Leisi,
H.-Ch. Schröder,
Z. G. Zhao,
D. Chatellard,
J.-P. Egger,
E. Jeannet,
E. C. Aschenauer,
K. Gabathuler,
L. M. Simons,
A. J. Rusi El Hassani
Nuclear Physics A 01/1997; 617:526. · 1.54 Impact Factor
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A. Badertscher,
E. C. Aschenauer, M. Bogdan,
D. Chatellard,
J. -P. Egger,
K. Gabathuler,
P. F. A. Goudsmit,
E. Jeannet,
H. J. Leisi,
E. Matsinos,
A. J. Rusi El Hassani,
H. Ch. Schröder,
D. Siggl,
L. M. Simons,
Z. G. Zhao
01/1970: pages 238-240;
