P. Ronsheim

IBM, Armonk, New York, United States

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Publications (39)29.94 Total impact

  • Microscopy and Microanalysis 07/2010; 16:568-569. DOI:10.1017/S143192761005587X · 1.76 Impact Factor
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    ABSTRACT: A new combination of long millisecond (1-2.5 ms) flash anneal at high peak temperature(1200-1300°C) and a new absorber with low deposition temperature (
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    ABSTRACT: We have demonstrated that off-axis holography can be realized in TEM and applied to 2-D quantitative analysis of p-n junctions in submicron devices. Examples of the recent work showed that millisecond laser anneal does not cause lateral diffusion of As extension implant in n-FET devices. The reduction of potential variation across depletion region in n-FET devices with carbon co-implant was directly observed. In combination with the SIMS data it is attributed to suppression of boron halo diffusion. The short channel device characteristics can be improved if carbon co-implant is used.
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    Solid State Devices and Materials, Ibaraki, Japan; 09/2008
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    ABSTRACT: Twisted direct silicon bonded (DSB) substrate demonstrates a higher hole mobility advantage over (110) bulk substrate for PFET. The mobility shows a (110) layer thickness dependence with the thinner DSB layer having a higher hole mobility. 25% on-current improvement is obtained for thin DSB PFETs at long channel (L<sub>g</sub>= 2 mum), 10% higher at short channel (L<sub>g</sub> = 36 nm) compared to (110) bulk PFETs. Moreover, we found that the thinner DSB shows better V<sub>t</sub> roll-off characteristics. On the other hand, NFETs on DSB are as good as (100) bulk NFETs. Thin DSB substrate demonstrates 11% faster ring oscillator speed over thick DSB substrate and 30% faster over (100) bulk due to higher mobility and lower capacitance.
    VLSI Technology, 2008 Symposium on; 07/2008
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    ABSTRACT: Various methods of generating high stress in thin plasma enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) films are reported. Besides the mainstream variation of plasma power and other process parameters, novel techniques such as creation of high density layers in multilayer PECVD structures or exposure of SiN films to ultraviolet radiation are shown to increase intrinsic film stress. Thin PECVD SiN films have been analyzed by a variety of analytical techniques including Fourier transform infrared spectroscopy, x-ray reflectivity (XRR), time of flight secondary ion mass spectrometry, and transmission electron microscopy to collect data on bonding, density, chemical composition, and film thickness. The level of bonded hydrogen as well as film density has been found to correlate with film stress. Creation of multilayer structures and high density layers help to build up more stress compared to a standard single layer film deposition. Both the density and number of layers in a film, characterized by XRR, affect the stress. Higher density layers affect diffusion profiles and show impurity oscillations corresponding to a multilayer film structure. Ultraviolet cure allows the film to achieve higher level of tensile stress at relatively low temperatures (400–500 °C), comparable to the result of film high temperature annealing.
    Journal of Vacuum Science & Technology A Vacuum Surfaces and Films 05/2008; 26(3). DOI:10.1116/1.2906259 · 2.14 Impact Factor
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    ABSTRACT: Importance of effects of charging and sample thickness variation across depletion region is discussed using one-dimensional p-n junction in bulk Si and silicon-on-insulator (SOI) structures prepared by mechanical polishing. It is shown that good correlation between results of electron holography and secondary ion mass spectroscopy can be achieved without consideration of “dead layers.” Analysis of laser annealed n-type field-effect transistor (n-FET) devices in SOI structures showed that laser annealing does not cause lateral dopant diffusion of arsenic to resolution of electron holography. It is demonstrated that junction overlap can be achieved with “laser-only” integration scheme. Examples are given on how electron holography can provide insight into integration scheme for development of a p-FET device with embedded SiGe source/drain regions and evaluation of effect of proximity of shallow trench isolation on dopant depletion.
    Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 01/2008; 26(1). DOI:10.1116/1.2834558 · 1.36 Impact Factor
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    ABSTRACT: Elements such as sodium and potassium can contaminate oxides in semiconductor devices, including buried oxides in Silicon-On-Insulator (SOI) devices. Common fabrication processes use chemicals which contain such contaminants - an example being chemical-mechanical polish slurries - which can contain high levels of sodium or potassium. When charge contamination, particularly mobile charge contamination, gets under SOI devices, it can shift characteristics such as threshold voltage, and when this happens in sensitive analog circuits, it can lead to yield and reliability issues. We will describe an example and suggest possible layout mitigation strategies.
    Advanced Semiconductor Manufacturing Conference, 2007. ASMC 2007. IEEE/SEMI; 07/2007
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    ABSTRACT: Ultra thin layers of magnesium containing cap layers are deposited on Hf based dielectrics prior to deposition of the TiN/Poly-Si electrode stack [1] to achieve band-edge (BE) high-kappa/metal nMOSFETs with good mobility (190 cm<sup>2</sup>/Vs @ 1 MV/cm) at T<sub>inv</sub> (1.45 nm), in a gate first process flow. It is shown that V<sub>t</sub> can be modulated anywhere between midgap and band edge by changing the cap layer thickness. Short channel devices with band edge characteristics are demonstrated down to 40 nm.
    VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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    ABSTRACT: Not Available
    Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE; 02/2006
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    ABSTRACT: We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm<sup>2</sup>/Vs @ 1MV/cm) at the thinnest T<sub>inv</sub> (1.4 nm) reported to date. These stacks are formed by capping HfO<sub>2</sub> with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the V<sub>t</sub>/V <sub>fb</sub> from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET V<sub>t</sub> shift are discussed
    VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on; 01/2006
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    ABSTRACT: We have investigated the impact of laser spike anneal (LSA) on the performance of ultra-thin SOI MOSFETs. LSA was found to significantly reduce the parasitic external resistance in UTSOI devices. Reduced external resistance in conjunction with improved gate activation resulted in a substantial improvement in nFET performance. A conventional spike RTA followed by LSA at 1300C enhances nFET drive current, ION, by 20% and the effective drive current, IOFF, by 30% (at IOFF equiv 1 muA/mum). The RTA+LSA approach was found to have a smaller impact on pFET performance. This is attributed to boron loss due to segregation into the buried oxide (BOX) during the RTA. The RTA+LSA process also resulted in improved AC performance (~ 10% improvement in ring oscillator stage delay at fixed leakage current) compared to an RTA-only process. We have found that an LSA-only process significantly suppresses boron segregation and increases dopant activation, resulting in a 50% reduction in the p-type sheet resistance when compared to a conventional high temperature RTA-only process. The introduction of LSA provides a path for high performance UTSOI CMOS
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2006; DOI:10.1109/VTSA.2006.251077
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    ABSTRACT: Thin gate oxide processes for advanced semiconductor manufacturing present many challenges at both the 90 and 65 nm technology nodes. In most cases the films are oxynitride materials (SiO<sub>x</sub>N<sub>y</sub>) constructed in single wafer tools clustered on the same common platform. The combination of discrete process chambers and the atomic dimensions of the dielectric puts a premium on film characterization and process control. The electrical specifications are severe with common values of ±1 Å leading to nitrogen and oxygen dose requirements of better than ±5E14 at/cm<sup>2</sup>. In the recent past difficulties maintaining those specifications have repeatedly lead to tool down situations and limited run paths. In the aftermath of those events, the investigations which followed exposed weaknesses in both the metrology and the qualification strategies used to characterize those processes. In this paper, a number of examples will be presented which illustrate the sensitivity of the composite process to excursions in any of its component steps. The relative sensitivities of different in-line measurement techniques (optical, electrical, and chemical) will be reported and the data used to illustrate the clear advantages of in-line compositional analysis.
    Advanced Thermal Processing of Semiconductors, 2005. RTP 2005. 13th IEEE International Conference on; 11/2005
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    ABSTRACT: Thin gate oxide processes for advanced semiconductor manufacturing present many challenges at both the 90 and 65 nm technology nodes. In most cases the films are oxynitride materials (SiO x N y ) constructed in single wafer tools clustered on the same common platform. The combination of discrete process chambers and the atomic dimensions of the dielectric puts a premium on film characterization and process control. The electrical specifications are severe with common values of ±1Ao leading to nitrogen and oxygen dose requirements of better than ±5E14 at/cm<sup>2</sup>. In the recent past difficulties maintaining those specifications have repeatedly lead to tool down situations and limited run paths. In the aftermath of those events, the investigations which followed exposed weaknesses in both the metrology and the qualification strategies used to characterize those processes. In this paper, a number of examples will be presented which illustrate the sensitivity of the composite process to excursions in any of its component steps. The relative sensitivities of different in-line measurement techniques (optical, electrical, and chemical) will be reported and the data used to illustrate the clear advantages of in-line compositional analysis.
    Advanced Thermal Processing of Semiconductors, 2005. RTP 2005. 13th IEEE International Conference on; 11/2005
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    ABSTRACT: Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.
    IEEE Transactions on Electron Devices 02/2005; 52(1-52):39 - 46. DOI:10.1109/TED.2004.841264(410) · 2.36 Impact Factor
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    ABSTRACT: Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN<sub>x</sub>) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN<sub>x</sub> for the NFET and ALD-WN<sub>x</sub> for the PFET. Much enhanced drive current (I<sub>d</sub>) and transconductance (G<sub>m</sub>) values, and reduced off current (I<sub>off</sub>) characteristics were attained with ALD-MN<sub>x</sub> gated devices over control poly-Si and PVD-MN<sub>x</sub> devices within controllable V<sub>t</sub> shifts. Excellent scalability of dual work function MN<sub>x</sub>/high-k gate stack was demonstrated: the EOT was down to 6.6Å with low leakage in a low thermal budget device scheme.
    VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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    ABSTRACT: SOI substrates with 300 mm diameter have recently become available for use in circuit development. Little is known at present about the quality of these substrates and how they compare to the well-established 200 mm substrates. This paper outlines several physical and electrical characterization techniques and their use in comparing both bonded and SIMOX 300 and 200 mm SOI material.
    Solid-State Electronics 06/2004; 48(6-48):1065-1072. DOI:10.1016/j.sse.2003.12.023 · 1.51 Impact Factor
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    ABSTRACT: Band-to-band tunneling was studied in ion-implanted P/N junction diodes with profiles representative of present and future silicon complementary metal–oxide–silicon (CMOS) field effect transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of capacitance versus voltage characteristics, and compared to secondary-ion mass spectroscopy analysis. When the tunneling current was plotted against the effective tunneling distance (tunneling distance corrected for band curvature) a quasi-universal exponential reduction of tunneling current versus, tunneling distance was found with an attenuation length of 0.38 nm, corresponding to a tunneling effective mass of 0.29 times the free electron mass (m0), and an extrapolated tunneling current at zero tunnel distance of 5.3×107 A/cm2 at 300 K. These results are directly applicable for predicting drain to substrate currents in CMOS transistors on bulk silicon, and body currents in CMOS transistors in silicon-on-insulator. © 2004 American Institute of Physics.
    Journal of Applied Physics 05/2004; 95(10):5800-5812. DOI:10.1063/1.1699487 · 2.19 Impact Factor
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    ABSTRACT: Band-to-band tunneling was studied experimentally in ion-implanted PN junction diodes with profiles representative of present and future silicon CMOS transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of CV characteristics, and compared to SIMS analysis. When tunneling current was plotted against distance (tunneling distance, corrected for band curvature) a quasi-universal exponential reduction of tunneling current vs. tunneling distance was found with an attenuation length of 0.38 nm, and an extrapolated tunneling current at zero tunnel distance of 5.3×10<sup>7</sup> A/cm<sup>2</sup> at 300 K. These results were used to estimate drain-substrate currents in future scaled CMOS, and it was concluded that it will be challenging to make the ITRS 2002 roadmap projections on leakage current for the low operating power and low standby power options without more innovation and device design changes.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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    ABSTRACT: We present enhanced 90 nm node CMOS devices on a partially depleted SOI with 40 nm gate length, featuring advanced process modules for manufacture, including RSD (raised source/drain), disposable spacer, final spacer for S/D doping and silicide proximity, NiSi, and thermally optimized MOL (middle-of-line) process. For the first time, we systematically designed silicide proximity in SOI and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 μA/um and 420 μA/um at Ioff = 40 nA/um with Vdd = 1.0 V, for NFET and PFET, respectively), significant reduction in effective gate oxide thickness under gate inversion by ∼1.2 Å and ∼2.1 Å, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004