[Show abstract][Hide abstract] ABSTRACT: We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (C<sub>sub</sub>) epitaxial Si:C and laser spike annealing (LSA) for increased C<sub>sub</sub> incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% C<sub>sub</sub> and 60% Rch reduction for 2.2% C<sub>sub</sub> are demonstrated.
[Show abstract][Hide abstract] ABSTRACT: This paper compares the performance and inter-die variability of doped and undoped channel multiple-gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrow-width planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar devices, conversions to undoped channel FinFETs is necessary. Furthermore, good short-channel control has to be maintained since undoped channel devices exhibit increase sensitivity to Tbody relative to doped channel FinFETs due to enhanced fully-depleted channel electrostatics
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
[Show abstract][Hide abstract] ABSTRACT: The semiconductor industry has maintained its historical exponential improvement in performance by aggressively scaling transistor dimensions. However, as devices approach sub-100-nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limitations imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhancing carrier mobility using biaxially tensile-stressed Si on relaxed SiGe on SOI and on bulk substrates has become a viable option to sustain continual drive current increase without traditional scaling. Although the addition of strained-Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained-Si CMOS devices include having uniform SiGe thickness, Ge composition, and strain distribution. These are required to maintain uniform device performance as well as low defect density for high minority carrier lifetimes and transconductance, as well as low surface roughness to minimize the impact of interface scattering on carrier mobilities. The parameters of interest in strained-Si CMOS technology include SiGe and Si channel thickness, Ge composition, strain, dislocation density, interface quality, and roughness. Nondestructive inline metrology techniques include spectroscopic ellipsometry for film thickness and Ge composition, X-ray reflectivity for thickness, density, and roughness measurements, X-ray fluorescence for Ge composition, UV-Raman spectroscopy for channel strain characterization, IR photoluminescence for defect detection, and X-ray diffraction for both Ge content and strain measurement. While most of these techniques are well established in the semiconductor -
industry, some will require development for application to volume manufacturing. This paper will focus on various metrology approaches used in strained-Si CMOS devices
IEEE Transactions on Semiconductor Manufacturing 12/2006; · 0.98 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper describes the novel stress engineering of SC-SSOI devices through the interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation. We have demonstrated a method of uniaxial stress relaxation with compressive capping layer (cESL) to achieve the desired stress configurations for enhanced short-channel SC-SSOIpMOS devices
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
[Show abstract][Hide abstract] ABSTRACT: In this paper we demonstrate for the first time a novel CMOS IT-FET (inverted T channel FET) architecture. We demonstrate well functional ITFET SRAM bit-cells. Vertical devices such as FinFET and planar ultra thin body devices have been shown to exhibit good short channel control and proposed for future device scaling. The ITFET is novel device architecture that takes advantage of both vertical and horizontal thin-body devices. A doped channel IT-FET process has been developed and is the focus of this paper. This technology can be scaled beyond 45nm technologies using undoped channels. An ITFET device comprises of an ultra thin body planar horizontal channels and vertical channels in a single device. The devices have multi-gate control around these channels to improve short channel control. A single device has multiple orientations and hence mobility enhancement of both (110) and (100) planes can be used optimally. The devices presented have 15nm planar horizontal thin body and 40nm vertical channels of 100nm height, 17Aring gate dielectric and 50nm gate length. These devices are especially useful in circuits that need ratioing such as in SRAM cells and a well functional SRAM cell is demonstrated
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
[Show abstract][Hide abstract] ABSTRACT: Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation have been optimized to achieve the desired stress configurations for enhancing both short-channel SSOI NMOS and PMOS devices
SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International; 01/2006
[Show abstract][Hide abstract] ABSTRACT: The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages
Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on; 01/2006
[Show abstract][Hide abstract] ABSTRACT: This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum process complexity. This work demonstrates the scalability of SC-SSOI and its advantages over pure biaxial and single uniaxial strained Si technologies
[Show abstract][Hide abstract] ABSTRACT: MIGFET devices have multiple gates to independently control the channel region. This allows for new device architectures and applications. This paper deals with three novel aspects discussed the first time I) Multi-fin MIGFET device with two independent gates capable of high current drives has been fabricated and demonstrated as a RF Mixer II) For the first time a MOSFET with three independent gates has been fabricated. These devices can be used in single transistor memories III) MIGFET has been used to characterize temperature effects on double gate devices in single electrode and independent gate modes. The three aspects discussed in the paper will have significant impact on future applications of these devices. The MIGFET can be integrated with double gate devices enabling novel analog circuits to scale with multi-gated digital CMOS in future digital CMOS transceiver (Single Chip Radio). The third independent gate in the MIGFET-T device enables novel memory architectures. Temperature characterization reveals the double gate Vt can be shifted both by temperature and by the second gate bias. This data enables compact modeling of temperature effects on independent gate devices to evaluate circuits that take advantage of this characteristic of the MIGFET.
[Show abstract][Hide abstract] ABSTRACT: In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
[Show abstract][Hide abstract] ABSTRACT: A promising high k material, lanthanum aluminum oxynitride (LAON), with excellent material and electronic properties is reported. The LAON film has good thermal stability and CMOS process compatibility at 1000 C. The LAON material has a dielectric constant of above 20, bandgap of 6.6 eV. Well-behaved I-V and C-V were obtained for 80 A LAON on silicon.
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on; 01/2004
[Show abstract][Hide abstract] ABSTRACT: In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO<sub>2</sub> gate dielectric at the 50-nm physical gate length. Symmetric V<sub>T</sub> is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I<sub>on</sub>=500 μA/μm and I<sub>off</sub>=10 nA/μm at V<sub>DD</sub>=1.2 V for nMOSFET and I<sub>on</sub>=212 μA/μm and I<sub>off</sub>=44 pA/μm at V<sub>DD</sub>=-1.2 V for pMOSFET, with a CET=30 Å and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V<sub>DD</sub>=1.2 V are also realized.
IEEE Transactions on Nanotechnology 01/2004; · 1.62 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Smooth, 4–6-nm thick hafnium oxide films were grown by atomic layer deposition from HfI4 or HfCl4 and H2O on SiO2/Si(1 0 0) substrates at 300 C. Non-uniform films were obtained on hydrogen-terminated Si(1 0 0). The stoichiometry of the films corresponded to that of HfO2. The films contained small amounts of residual chlorine and iodine. The films deposited on SiO2/Si(1 0 0) were amorphous, but crystallized upon annealing at 1000 C. In order to decrease the conductivity, the HfO2 films were mixed with Al2O3, and to increase the capacitance, the films were mixed with Nb2O5. The capacitance–voltage curves of the Hf–Al–O mixture films showed hysteresis. The capacitance–voltage curves of HfO2 films and mixtures of Hf–Al–Nb–O were hysteresis free.
Journal of Materials Science Materials in Electronics 04/2003; 14(5):361-367. · 1.97 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO2 at conventional temperatures (near 620 °C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO2 films using metal gates or silicon gates with low temperature deposition. However, depositing conventional CVD poly-Si gates directly onto Al2O3-capped, hafnium–silicate-capped, or physical vapor deposition (PVD) silicon-capped HfO2 resulted in the absence of large inhomogeneous poly-Si grains and well behaved capacitors with leakage reduction greater than 103 times compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO2 are attributed to a partial reduction of the HfO2 by the poly-Si deposition ambient. In the first case (1) the partial reduction occurs locally on the HfO2 surface, forming Hf–Six bond(s) which act as nucleation points for crystalline silicon growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.
[Show abstract][Hide abstract] ABSTRACT: Ta2O5, Ta–Nb–O, Zr–Al–Nb–O, and Zr–Al–O mixture films or solid solutions were grown on Si(1 0 0) substrates at 300 °C by atomic layer deposition. The equivalent oxide thickness of Ta2O5 based capacitors was between 1 and 3 nm. In Zr–Al–O films, the high permittivity of ZrO2 was combined with high resistivity of Al2O3 layers. The permittivity, surface roughness and interface charge density increased with the Zr content and the equivalent oxide thickness was between 2.0 and 2.5 nm. In the Zr–Al–Nb–O films the equivalent oxide thickness remained at 1.8–2.0 nm.
Journal of Non-Crystalline Solids 05/2002; 303(1):35–39. · 1.72 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: MOSFETs with a zirconium dioxide (ZrO<sub>2</sub>) gate dielectric
and poly-silicon gate were fabricated using a low temperature CMOS
process. Well-behaved transistor characteristics were obtained for
devices with sizes of 14 μm×1.4 μm or smaller. Devices 14
μm×14 μm or larger were found to be nonfunctional due to the
formation of Zr-silicide at the polySi-gate/Zr0<sub>2</sub> interface.
In this paper, we present results on the electrical and physical
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on; 02/2001
[Show abstract][Hide abstract] ABSTRACT: We report here for the first time the formation of an amorphous
oxide layer between the polysilicon gate and hafnium oxide (HfO<sub>2
</sub>) gate dielectric due to a lateral oxidation mechanism at the gate
edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm
MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv
of 25 Å with a leakage current 1000× lower than SiO<sub>2
</sub> was obtained for a 30 Å HfO<sub>2</sub>/12 Å
interfacial oxide stack. In this paper, we present results on the
physical and electrical characterization
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
[Show abstract][Hide abstract] ABSTRACT: There is an extensive effort in the transistor industry to develop
an alternative high-k gate dielectric to replace SiO<sub>2</sub> due to
tunneling limits. We have investigated the potential of crystalline
perovskite oxides (SrTiO<sub>3</sub> or STO) grown epitaxially over Si
as a gate dielectric. Transmission electron microscopy images show that
these epitaxial STO films have an interfacial amorphous layer <10
Å thick, that is mostly SiO<sub>2</sub>. Using tantalum nitride
(TaN) as a gate electrode, capacitors and MOSFETs were fabricated. Films
with an equivalent oxide thickness (EOT) of 9 Å were achieved from
a 100 Å STO layer yielding a dielectric constant of ~160.
Measurements on n- and p-channel MOSFETs show leakage currents at
±1 V beyond inversion of 15 mA/cm<sup>2</sup> and 25 mA cm<sup>2
</sup> respectively. Drive currents of 245 and 20 μA/μm were
realized for n- and p-channel devices. Calculated field mobilities were
221 cm<sup>2</sup>/V-sec for electrons and 62 cm<sup>2</sup>/V-s for
holes. The use of a gate stack that has a high-k material (STO) over a
low-k material (SiO<sub>2</sub>) may have some potential advantages over
a single medium-k layer
Device Research Conference, 2000. Conference Digest. 58th DRC; 02/2000
[Show abstract][Hide abstract] ABSTRACT: As microelectronics technology enters the deep-submicron arena,
fully depleted SOI (FDSOI) technology assumes a prominent position as a
potential solution to the problems associated with continued device
scaling. Some of the possible benefits of using FDSOI are improved
control of the transistor threshold voltage, lower junction capacitance,
higher device packing density, and latchup immunity (Maiti et al, 1998).
Fully depleted SOI devices with a metal gate (MGFDSOI) offer the
additional benefits of eliminating polysilicon depletion, allowing
thinner electrical gate dielectric thickness for the same physical
thickness along with reduced gate sheet resistance (Colinge, 1997). For
FDSOI structures with ultrathin (<200 Å) superficial silicon
thickness, epitaxially deposited Si is used to increase the available
depth for silicidation in the source-drain areas. This technique,
referred to as elevated source/drain (ESD), ensures lower contact
resistance with the device. This paper reports the results of physical
and electrical characterization of MGFDSOI device structures