Yeonbae Chung

Kyungpook National University, Daikyū, Daegu, South Korea

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Publications (14)4.29 Total impact

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    ABSTRACT: In this work, we demonstrate an experimental eDRAM utilizing logic-compatible N-style 2T gain cell on 130 nm CMOS technology. The memory bit-cell consists of a high-VTH write NMOS and a standard-VTH read NMOS. Combination of a low off-leakage device for write and a high mobility device for read provides much improved retention time and read performance in a compact bit area. The embedded macro operates with 32-kbit density, SRAM-like I/O interface and self-timed 128-row refresh. Measured retention time in typical 32- kbit dies at 1.2 V and room temperature exhibits an average of 2.1 ms.
    2015 IEEE International Conference on Electron Devices and Solid-State Circuits, Singapore; 06/2015
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    ABSTRACT: In this paper, we present a hybrid 2T gain cell based embedded DRAM with body-voltage controlled technique. The memory bit-cell is composed of a high-V TH write transistor and a standard-V TH read transistor. The negative cell-body toggle signal couples up the data '1' storage level after data write. It results in an enhanced data retention time. Moreover, the proposed technique exhibits much strong immunity on write disturbance since the subthreshold leakage through the write device is drastically reduced. Simulation results from a 64-kbit eDRAM implemented in a 130 nm triple-well logic CMOS technology demonstrate the effectiveness of the proposed embedded memory technique.
    SoC Design Conference (ISOCC), 2014 International, Jeju, South Korea; 11/2014
  • Weijie Cheng, Yeonbae Chung
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    ABSTRACT: The design and physical implementation of an embedded memory utilising bit-area efficient hybrid gain cell is presented. The memory cells in this work are composed of a high-threshold NMOS write transistor and a standard-threshold NMOS read transistor. The bit data are stored on the parasitic capacitances within the cells. Owing to the combination of low subthreshold-leakage write device and high mobility read device, this NMOS-based hybrid 2T gain cell exhibits much improved data retention and read performance in a compact bit area. The memory arrays operate with a logic-compatible supply voltage; SRAM-like I/O interface; chip-select-controlled 128-row refresh; and non-destructive read with speed comparable with 6T SRAM, but 65% smaller cell area. Measurement results from a 32 kbit pseudo-SRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed embedded memory techniques.
    IET Circuits Devices & Systems 03/2014; 8(2):107-117. DOI:10.1049/iet-cds.2013.0234 · 0.91 Impact Factor
  • Weijie Cheng, Jeong-Wook Cho, Yeonbae Chung
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    ABSTRACT: In this work, we present an embedded DRAM utilizing logic-compatible 2T gain cell. The memory cells are composed of a high-VTH write NMOS and a standard read NMOS. Due to the combination of low off-leakage write device and high mobility read device, this NMOS-based hybrid gain cell provides much improved data retention and read performance. At 1.2 V and 85 °C, the proposed bit-cell achieves 1.1× longer standby retention and 4.4× longer write disturbance retention compared to the PMOS-only 2T cell. The memory arrays operate with a logic-compatible supply voltage; /CS controlled 128-row refresh; and nondestructive read with speed comparable to 6T SRAM but 65 % smaller cell area. Design results from a test chip in a 130 nm logic CMOS technology exhibit the effectiveness of the proposed embedded memory techniques.
    SoC Design Conference (ISOCC), 2012 International; 01/2012
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    ABSTRACT: In this work, we present a novel 8T SRAM cell that enhances the stability of built-in data storage elements. During a read operation, the proposed cell suppresses a noise-vulnerable '0' node rising, and hence exhibiting near-ideal butterfly curve essential for robust SRAM bit-cell design. The cell itself bears an improved variability tolerance which gives much tight stability distribution across skewed process corners. Implementation results in a 130 nm CMOS technology show that the 8T cell achieves almost 100 % higher read stability compared to the standard 6T cell. The data write-ability and stability tolerance provided with the new cell are also verified under process and temperature variations.
    Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on; 01/2012
  • Jung-Hyun Kim, Yeonbae Chung
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    ABSTRACT: A piecewise-linear based behavioral model for ferroelectric capacitors is presented. The model simply consists of two linear capacitors, two diodes and two dc voltage sources. By adjusting empirical parameters to fit the measured hysteresis loops, the model repeats the ferroelectric DC characteristics in accord with the measurements. In addition, the model predicts quite well the transient characteristics of a ferroelectric memory. It is shown, from the standpoint of practical application, that the proposed model is very suitable for use in simulations of the ferroelectric memory circuits.
    Integrated Ferroelectrics 09/2010; 96(2008):131-139. DOI:10.1080/10584580701748737 · 0.37 Impact Factor
  • Jung-Chan Lee, Yeonbae Chung
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    ABSTRACT: In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V DD = 0.9 V, approximately 10% higher peak power efficiency at V DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.
    International Journal of Electronics 03/2010; 97(3):273-283. DOI:10.1080/00207210903289367 · 0.75 Impact Factor
  • Yeonbae Chung, Weijie Cheng
    IEICE Electronics Express 01/2010; 7(15):1145-1151. DOI:10.1587/elex.7.1145 · 0.39 Impact Factor
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    ABSTRACT: In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30% reduction in read power and 42% reduction in write power compared to the conventional 6-transistor (6T) SRAM.
  • Yeonbae Chung, Seung-Ho Song
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    ABSTRACT: This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.
    Microelectronics Journal 06/2009; 40(6-40):944-951. DOI:10.1016/j.mejo.2008.11.063 · 0.92 Impact Factor
  • Jin-Young Park, Yeonbae Chung
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    ABSTRACT: A new charge pump circuit feasible for the implementation with standard CMOS logic process is proposed. The proposed charge pump employs complementary dual charge-transfer paths and a simple two-phase clock. The charge transfer switches in each pumping stage can completely transfer the charges from the present stage to the next stage without suffering threshold voltage drop. Thus, the power efficiency is higher than that of the traditional schemes. The output voltage of charge pump circuit with eight stages is 8 V at 1.2 V power supply. The simulations demonstrate that the proposed charge pump exhibits a better pumping efficiency and a larger current drivability over the previous one.
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
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    ABSTRACT: This work presents a low voltage SRAM design technique to increase the operating margin. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 0.18-mum CMOS 256-Kbit SRAM macro has been fabricated with the proposed technique. The chip operates with 50 MHz at 0.8 V supply voltage. It consumes a power of 65 muW/MHz. Measurement shows that the proposed SRAM configuration achieves a reduction by 87% in bit-error rate while operating with 43% higher clock frequency compared with that of conventional SRAM.
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
  • Jung-Chan Lee, Jin-Young Park, Yeonbae Chung
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    ABSTRACT: In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations shows that the proposed charge pump exhibits the higher output voltage, the larger output current, and thus a better power efficiency over the traditional twin-well charge pumps.
  • Source
    Yeonbae Chung, Sang-Won Shim
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    ABSTRACT: This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18 mu m CMOS 256-kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 mu W/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.
    Etri Journal 08/2007; 29(4):457-462. DOI:10.4218/etrij.07.0106.0298 · 0.95 Impact Factor

Publication Stats

30 Citations
4.29 Total Impact Points

Institutions

  • 2008–2014
    • Kyungpook National University
      • • Department of Electrical Engineering
      • • School of Computer Science and Engineering
      Daikyū, Daegu, South Korea