Yeonbae Chung

Kyungpook National University, Taegu, Daegu, South Korea

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Publications (5)0.51 Total impact

  • Jung-Chan Lee, Yeonbae Chung
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    ABSTRACT: In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V DD = 0.9 V, approximately 10% higher peak power efficiency at V DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.
    International Journal of Electronics 03/2010; 97(3):273-283. · 0.51 Impact Factor
  • Yeonbae Chung, Seung-Ho Song
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    ABSTRACT: This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.
    Microelectronics Journal. 01/2009;
  • Jin-Young Park, Yeonbae Chung
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    ABSTRACT: A new charge pump circuit feasible for the implementation with standard CMOS logic process is proposed. The proposed charge pump employs complementary dual charge-transfer paths and a simple two-phase clock. The charge transfer switches in each pumping stage can completely transfer the charges from the present stage to the next stage without suffering threshold voltage drop. Thus, the power efficiency is higher than that of the traditional schemes. The output voltage of charge pump circuit with eight stages is 8 V at 1.2 V power supply. The simulations demonstrate that the proposed charge pump exhibits a better pumping efficiency and a larger current drivability over the previous one.
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work presents a low voltage SRAM design technique to increase the operating margin. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 0.18-mum CMOS 256-Kbit SRAM macro has been fabricated with the proposed technique. The chip operates with 50 MHz at 0.8 V supply voltage. It consumes a power of 65 muW/MHz. Measurement shows that the proposed SRAM configuration achieves a reduction by 87% in bit-error rate while operating with 43% higher clock frequency compared with that of conventional SRAM.
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
  • Jung-Chan Lee, Jin-Young Park, Yeonbae Chung
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations shows that the proposed charge pump exhibits the higher output voltage, the larger output current, and thus a better power efficiency over the traditional twin-well charge pumps.
    01/2008;

Publication Stats

18 Citations
0.51 Total Impact Points

Institutions

  • 2008–2010
    • Kyungpook National University
      • School of Computer Science and Engineering
      Taegu, Daegu, South Korea