-
[show abstract]
[hide abstract]
ABSTRACT: Polarity dependence of charge trapping in poly-Si gate HfO<sub>2</sub> MOSFETs has been systematically studied. It is shown that both the stress-induced threshold voltage shift (ΔV<sub>th</sub>) and the transconductance degradation (ΔG<sub>m</sub>) are worse in nMOSFETs than in pMOSFETs. For substrate injection in nMOSFETs, electron trapping occurs at the n-poly/HfO<sub>2</sub> interface and/or in bulk HfO<sub>2</sub>, whereas for gate injection in pMOSFETs hole trapping near the Si substrate is observed. These results strongly suggest the poly-Si/HfO<sub>2</sub> interface should play an important role in hot carrier induced degradation in HfO<sub>2</sub> gated nMOSFETs.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
-
W.J. Taylor,
E. Verret,
C. Capasso,
Jen-Yee Nguyen,
Le Boi La,
E. Luckowski,
A Martinez,
C. Happ,
J Schaeffer,
M Raymond, P. Tobin
[show abstract]
[hide abstract]
ABSTRACT: It is well accepted that one of the key parasitic resistances in ULSI transistors is the contact resistance between the silicide and the doped source/drain. In this paper, we investigate the individual components of this parameter. We show that the contact length is already a contributor at the 90 and 65nm nodes. Changing active doping in the Si via dose/energy modulations can reduce contact resistance in a low temperature flow, but not sufficiently to match results at high temperature. The largest knob is barrier height, leading some to consider moving to 2 different materials for contact to N+ and P+ regions (to replace a single silicide) which, although more complicated for processing may provide significant reductions in resistance. Using modifications to standard test structures and evaluation techniques, it becomes feasible to isolate the individual components of resistance, and to make significant progress in reducing this resistance.
Junction Technology, 2004. IWJT '04. The Fourth International Workshop on; 04/2004
-
Bich-Yen Nguyen,
A. Thean,
T. White,
A. Vandooren,
M. Sadaka,
L. Mathew,
A. Barr,
S. Thomas,
M. Zalava,
Da Zhang, [......],
S. Kalpat,
L. Prabhu,
V. Kaushik,
Y. Du,
T. Dao,
M. Mendicino,
M. Orlowski, P. Tobin,
J. Mogab,
S. Venkatesan
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
-
[show abstract]
[hide abstract]
ABSTRACT: The effects of hot-carrier injection on the reliability of both n-and p-channel MOSFETs with HfO<sub>2</sub> as the gate dielectric is reported in this paper. The polySi/HfO<sub>2</sub>/Si MOS structure illustrates possible structural differences between the polySi/HfO<sub>2</sub> interface and the HfO<sub>2</sub>/substrate-Si interface. Electron trapping probability is dominant in nMOSFET during constant-voltage stress over the entire voltage range, while in pMOSFET, hole trapping probability is appreciable above the stress voltage of -2.6 V. Gate leakage currents are measured using a carrier separation technique. Stress voltage dependence of electron trapping probability diminishes as an ultra-thin SiN<sub>x</sub> layer is added in between HfO<sub>2</sub> and the poly silicon gate.
Semiconductor Device Research Symposium, 2003 International; 01/2004
-
C. Hobbs,
L. Fonseca,
V. Dhandapani,
S. Samavedam,
B. Taylor,
J. Grant,
L. Dip,
D. Triyoso,
R. Hegde,
D. Gilmer,
R. Garcia,
D. Roan,
L. Lovejoy,
R. Rai,
L. Hebert,
H. Tseng,
B. White, P. Tobin
[show abstract]
[hide abstract]
ABSTRACT: We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub>, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
-
D. C. Gilmer,
R. Hegde,
R. Cotton,
R. Garcia,
V. Dhandapani,
D. Triyoso,
D. Roan,
A. Franke,
R. Rai,
L. Prabhu,
C. Hobbs,
J. M. Grant,
L. La,
S. Samavedam,
B. Taylor,
H. Tseng, P. Tobin
[show abstract]
[hide abstract]
ABSTRACT: Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO <sub>2</sub> and Al <sub>2</sub> O <sub>3</sub> capped HfO <sub>2</sub> gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO <sub>2</sub> results in electrical properties much worse compared to similar HfO <sub>2</sub> films using platinum metal gates. However, depositing CVD silicon gates directly onto Al <sub>2</sub> O <sub>3</sub> capped HfO <sub>2</sub> showed greater than a 10<sup>4</sup> times reduction in gate leakage compared to the poly-Si/HfO <sub>2</sub> and poly-Si/SiO <sub>2</sub> controls of similar electrical thickness. © 2002 American Institute of Physics.
Applied Physics Letters 09/2002; · 3.84 Impact Factor
-
C. Hobbs,
L. Dip,
K. Reid,
D. Gilmer,
R. Hegde,
T. Ma,
B. Taylor,
B. Cheng,
S. Samavedam,
H. Tseng, [......],
M. Rendon,
L. Prabhu,
R. Rai,
S. Bagchi,
J. Conner,
S. Backer,
F. Dumbuya,
J. Locke,
D. Workman, P. Tobin
[show abstract]
[hide abstract]
ABSTRACT: MOSFETs with a zirconium dioxide (ZrO<sub>2</sub>) gate dielectric
and poly-silicon gate were fabricated using a low temperature CMOS
process. Well-behaved transistor characteristics were obtained for
devices with sizes of 14 μm×1.4 μm or smaller. Devices 14
μm×14 μm or larger were found to be nonfunctional due to the
formation of Zr-silicide at the polySi-gate/Zr0<sub>2</sub> interface.
In this paper, we present results on the electrical and physical
characterization
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on; 02/2001
-
[show abstract]
[hide abstract]
ABSTRACT: Extensive simulations were performed to evaluate the impact of the
gate workfunction on the sub-80-nm PD and FD SOI device performance. The
optimal gate workfunction for the 50 nm technology node is 0.2 eV below
(above) the conduction (valence) band edge of silicon for NMOS (PMOS).
Midgap gates are not suitable for PD SOI CMOS due to the severe
short-channel effects, but are desirable for FD SOI CMOS
SOI Conference, 2001 IEEE International; 02/2001
-
C. Hobbs,
H. Tseng,
K. Reid,
B. Taylor,
L. Dip,
L. Hebert,
R. Garcia,
R. Hegde,
J. Grant,
D. Gilmer, [......],
V. Dhandapani,
M. Azrak,
L. Prabhu,
R. Rai,
S. Bagchi,
J. Conner,
S. Backer,
F. Dumbuya,
B. Nguyen, P. Tobin
[show abstract]
[hide abstract]
ABSTRACT: We report here for the first time the formation of an amorphous
oxide layer between the polysilicon gate and hafnium oxide (HfO<sub>2
</sub>) gate dielectric due to a lateral oxidation mechanism at the gate
edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm
MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv
of 25 Å with a leakage current 1000× lower than SiO<sub>2
</sub> was obtained for a 30 Å HfO<sub>2</sub>/12 Å
interfacial oxide stack. In this paper, we present results on the
physical and electrical characterization
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
-
[show abstract]
[hide abstract]
ABSTRACT: As microelectronics technology enters the deep-submicron arena,
fully depleted SOI (FDSOI) technology assumes a prominent position as a
potential solution to the problems associated with continued device
scaling. Some of the possible benefits of using FDSOI are improved
control of the transistor threshold voltage, lower junction capacitance,
higher device packing density, and latchup immunity (Maiti et al, 1998).
Fully depleted SOI devices with a metal gate (MGFDSOI) offer the
additional benefits of eliminating polysilicon depletion, allowing
thinner electrical gate dielectric thickness for the same physical
thickness along with reduced gate sheet resistance (Colinge, 1997). For
FDSOI structures with ultrathin (<200 Å) superficial silicon
thickness, epitaxially deposited Si is used to increase the available
depth for silicidation in the source-drain areas. This technique,
referred to as elevated source/drain (ESD), ensures lower contact
resistance with the device. This paper reports the results of physical
and electrical characterization of MGFDSOI device structures
SOI Conference, 2000 IEEE International; 02/2000
-
C. Hobbs,
R. Hegde,
B. Maiti,
H. Tseng,
D. Gilmer, P. Tobin,
O. Adetutu,
F. Huang,
D. Weddington,
R. Nagabushnam,
D. O'Meara,
K. Reid,
L. La,
L. Grove,
M. Rossow
[show abstract]
[hide abstract]
ABSTRACT: We report here for the first time the integration of sub-quarter
micron CMOSFETs on bulk silicon using an oxidized metal gate dielectric.
A polysilicon capped physical vapor deposited (PVD) titanium nitride
(TiN) was used as the gate electrode. Well behaved MOSFET
characteristics were obtained. In this paper, we present results on the
physical and electrical characterization of titanium dioxide (TiO<sub>2
</sub>) produced by oxidizing a thin PVD Ti film
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
-
J. Chen,
B. Maiti,
D. Connelly,
M. Mendicino,
F. Huang,
O. Adetutu,
Y. Yu,
D. Weddington,
W. Wu,
J. Candelaria,
D. Dow, P. Tobin,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: We report here for the first time a 0.18 μm fully-depleted SOI
process with PVD TiN metal gate. As midgap work function metal gate and
very light channel doping were used, threshold voltage can be easily
controlled in ±300 mV to ±500 mV range and on-wafer
V<sub>t</sub> variation was only about ±5 mV. Short channel
effects can be further improved when silicon film thickness is thinner
than 300 Å. Subthreshold slope was kept below 75 mV/dec even for
subnominal devices and V<sub>t</sub> roll-offs for both N- and P-MOSFETs
were very small
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
-
D.C. Gilmer,
R. Hegde,
R. Cotton,
J. Smith,
L. Dip,
R. Garcia,
V. Dhandapani,
D. Triyoso,
D. Roan,
A. Franke,
R. Rai,
L. Prabhu,
C. Hobbs,
J.M. Grant,
L. La,
S. Samavedam,
B. Taylor,
H. Tseng, P. Tobin
[show abstract]
[hide abstract]
ABSTRACT: Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO2 at conventional temperatures (near 620 °C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO2 films using metal gates or silicon gates with low temperature deposition. However, depositing conventional CVD poly-Si gates directly onto Al2O3-capped, hafnium–silicate-capped, or physical vapor deposition (PVD) silicon-capped HfO2 resulted in the absence of large inhomogeneous poly-Si grains and well behaved capacitors with leakage reduction greater than 103 times compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO2 are attributed to a partial reduction of the HfO2 by the poly-Si deposition ambient. In the first case (1) the partial reduction occurs locally on the HfO2 surface, forming Hf–Six bond(s) which act as nucleation points for crystalline silicon growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.
Microelectronic Engineering 69:138-144. · 1.56 Impact Factor
