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Journal of The Electrochemical Society 01/2012; 159(3):H208-H213. · 2.59 Impact Factor
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Diffusion and Defect Data Part B (Solid State Phenomena). 01/2012; 187:207-10.
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Yong Kong Siew,
J. Versluijs,
E. Kunnen,
I. Ciofi,
W. Alaerts,
H. Dekkers,
H. Volders,
S. Suhard,
A. Cockburn,
E. Sleeckx,
E. Van Besien, H. Struyf,
M. Maenhoudt,
A. Noori,
D. Padhi,
K. Shah,
V. Gravey,
G. Beyer
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ABSTRACT: Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).
Interconnect Technology Conference (IITC), 2010 International; 07/2010
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ABSTRACT: The effect of ash chemistry on dielectric constant of blanket and patterned low-k was studied using a near-field scanning probe microwave microscope, known commercially as NeoMetriK<sup>TM</sup> technology. Two common photoresist ash approaches with the same etch sequence were studied: plasma assisted sublimation of photoresist at elevated temperature and ion-assisted ash at room temperature. The results for blanket low-k agree well with the FTIR and water source ellipsometric porosimetry (WEP) measurements. The amount of sidewall damage measured in patterned structures before metallization confirms the expected trends.
Interconnect Technology Conference, 2009. IITC 2009. IEEE International; 07/2009
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Y. Travaly,
J. van Aelst,
V. Truffert,
P. Verdonck,
T. Dupont,
E. Camerotto,
O. Richard,
H. Bender,
C. Kroes,
D. de Roest, [......],
E. Kesters,
M. van Cauwenberghe,
J. Beynet,
S. Kaneko, H. Struyf,
M. Baklanov,
K. Matsushita,
N. Kobayashi,
H. Sprey,
G. Beyer
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ABSTRACT: Interconnect solutions for advanced technology nodes using PECVD techniques for low-k deposition require the use of porogen-based process with post deposition UV cure. By using two different UV cure lamps (A, B) in combination with different porogen loads, three different micro-porous low-k films are developed: Aurora® ELK HM (k~2.5; porosity (P) ~25%), Aurora® ELK A (k~2.3; P~34%) and Aurora® ELK B (k~2.2; P~37%). Integrating these materials is complex and challenging. We discuss key factors that are instrumental to the extension of a metal hard mask (MHM)-based integration scheme to these 3 low-k films. Our findings: (I) for sub-100nm dimensions, patterning and low-k interactions affect the dynamic of organic residue formation and thereby impact electrical yield; (II) choosing the right ash, etch and clean sequence is mandatory to control plasma damage, profile, residues and corrosion on top of the MHM; (III) Cu reduction plasmas must be adjusted when porosity is increased to mitigate field damage.
Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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S. Demuynck,
Z. Tokei,
C Zhao,
J. de Marneffe, H. Struyf,
W. Boullart,
M.O. de Beeck,
L. Carbonell,
N. Heylen,
J. Vaes,
G.P. Beyer,
S. Vanhaelemeersch,
R. Sadjadi,
H Zhu,
P. Cirigliano,
J.S. Kim,
J. Vertommen,
B. Coenegrachts,
E. Pavel,
A. Athayde
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ABSTRACT: In this paper we demonstrate the feasibility of integrating a technique for shrinking the lithography-defined feature size by using a plasma process prior to etch. The technique is based on a sequential deposition and selective removal of a polymer coating formed on the top and sidewalls of the developed resist. This method can be applied to both contacts and trenches and allows tuning of the shrink amount. Yielding damascene trenches down to 45 nm were obtained, shrunk from a 85 nm print, while functional 100 nm contacts were formed starting from a 150 nm print. In both cases excellent within-wafer non-uniformities were achieved.
Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on; 11/2007
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A. Ikeda,
Y. Travaly,
A. Humbert,
R.J.O.M. Hoofman,
Y.L. Li,
Zs. Tokei,
F. Iacopi,
J. Michelon,
C. Bruynseraede,
M. Willegems, [......],
M. Kaiser,
R.G.R. Weemaes,
G. Verheyden,
N. Kemeling,
A. Fukazawa,
N. Matsuki,
H. Sprey,
I. Ciofi,
G. Beyer,
M. Van Hove
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ABSTRACT: Single damascene (SD) Cu/Aurora<sup>reg</sup> ULK interconnects with a minimum spacing of 50nm are achieved by using a metal hard mask (MHM) integration scheme, which enables to perform the resist ash before dielectric etch. This patterning scheme is used in combination with a low damage etch technique based on sidewall protection. Interconnect performance and reliability can be further improved by using Aurora<sup>reg</sup> ULK high modulus (HM), a low-k film with a reduced diffusivity as compared to Aurora ULK, and a comparable k-value of 2.7. The MHM approach results in a limited increase in integrated k-value by 0.1 for ULK HM vs. 0.3 for Aurora<sup>reg</sup> ULK. The median time dependent dielectric breakdown (TDDB) lifetime is well above the 10 years criterion for spacings down to the 50nm. Finally, the MHM integration scheme enabled fabrication of dual damascene interconnects with Aurora<sup>reg</sup> ULK HM
Interconnect Technology Conference, 2006 International; 07/2006
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ABSTRACT: A surface acoustic wave technique was successfully applied for monitoring modification/damage of low-k dielectrics resulting from plasma-based patterning in a non-destructive and non-contact fashion. It is shown that this technique can be used to assess and compare dielectric damage, due to different processing conditions, in patterned structures.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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ABSTRACT: Etch and strip plasma-induced damage is well-known to make the integration of sensitive low-k dielectrics in damascene schemes cumbersome. In this paper, three metal hardmask-based single-damascene patterning approaches are compared. EFTEM analysis and integrated k-value extraction show that the use of a metal hardmask-based scheme with optimized plasma chemistries and etch/strip sequencing results in very low damage to the SiOC(H) low-k dielectric.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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ABSTRACT: This presentation is an overview of clean/strip processing for low Cu/low-k technology. The paper starts with a brief analysis of dry etch processes that determine the issues in subsequent processes; in the case of porous low-k dielectrics, etch conditions must be carefully optimized to find an optimal balance between the polymer formation and plasma damage of low-k dielectrics. The presentation includes recent results related to dry and wet cleaning, plasma damage, and stability of low-k films. The wet cleaning of solutions using supercritical CO<sub>2</sub>(SCCO<sub>2</sub>)IPA/water mixtures and special surfactants will also be analyzed. Results obtained by different advanced techniques like FTIR, XPS, ellipsometric porosimetry (EP), energy filtered TEM (EFTEM), TOF SIMS etc have been used to characterize the residues, plasma damage and cleaning efficiency and they will be analyzed during the presentation.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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Electrochemical and Solid-State Letters 01/2004; 7(9):F49-F53. · 2.00 Impact Factor
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Electrochemical and Solid-State Letters 01/2004; 7(9):F49-F53. · 2.00 Impact Factor
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R. Caluwaerts,
M. Van Hove,
G. Beyer,
R.J.O.M. Hoofman, H. Struyf,
G.J.A.M. Verheyden,
J. Waeterloos,
Z. Tokei,
F. Iacopi,
L. Carbonell,
Q.T. Le,
A. Das,
I. Vos,
S. Demuynck,
K. Maex
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ABSTRACT: The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
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J. Van Olmen,
W. Wu,
M. Van Hove,
Y. Travaly,
S.H. Brongersma,
B. Eyckens,
M. Maenhoudt,
J. Van Aelst, H. Struyf,
S. Demuynck,
Z. Tokei,
I. Vervoort,
B. Sijmus,
I. Vos,
I. Ciofi,
M. Stucchi,
K. Maex,
F. Iacopi
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ABSTRACT: This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond (Applied Materials) dielectric (k=2.85). Optical lithography (193 nm) with off-axis illumination was used to print the trenches. Integration issues are discussed, and resistance and RC delay data are presented. The method is applied to study the resistivity for sub 100 nm copper lines.
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
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W. D. Gray,
M. J. Loboda,
J. N. Bremmer, H. Struyf,
M. Lepage,
M. Van Hove,
R. A. Donaton,
E. Sleeckx,
M. Stucchi,
F. Lanckmans,
T. Gao,
W. Boullart,
B. Coenegrachts,
M. Maenhoudt,
S. Vanhaelemeersch,
H. Meynen,
K. Maex
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ABSTRACT: The semiconductor grade organosilicon gas trimethylsilane (Dow Corning Z3MS) can be used to deposit unique amorphous hydrogenated
silicon carbide (α-SiC:H)-based alloy films that exhibit desirable properties such as chemical resistance, low stress, low
permittivity, and low leakage. These film characteristics are ideal for applications in Cu-damascene interconnect technology.
In this work, the results of a comprehensive study of Z3MS plasma enhanced chemical vapor deposition (PECVD) dielectric films
are reported where all depositions were performed in commercial production PECVD equipment. Processing for α-SiC:H films deposited
from Z3MS/He mixtures was optimized for deposition rate, uniformity, and permittivity. The processing parameters can be tuned
for relative permittivity down to
making α-SiC:H an attractive substitute for PECVD silicon oxide or silicon nitride. Using mixtures of Z3MS and
precursors, α-SiCO:H films were deposited with very high deposition rates and film permittivity as low as
These films have been applied in damascene technology. Physical properties and stability of blanket films were studied. Measurement
of relative permittivity, leakage current, and breakdown voltage was performed on metal/dielectric/metal structures. Fourier
transform infrared, X-ray photoelectron, and high-energy ion scattering spectrometry were used to determine bonding and film
compositions. Integration issues related to deep ultraviolet lithography, dry etch, strip, and metallization are discussed.
Optimized film processes were integrated into 0.18 μm Cu damascene interconnect process technology and the electrical results
were compared to standard PECVD oxide. The results of these studies indicate that the device performance improvements inferred
from the blanket film properties can be realized in fully integrated interconnect structures. © 2003 The Electrochemical Society.
All rights reserved.
Journal of The Electrochemical Society. 06/2003; 150(7):G404-G411.
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T Kokubo,
A. Das,
Y. Furukawa,
I. Vos,
F. Iacopi, H. Struyf,
J.V. Aelst,
M. Maenhoudt,
Z. Tokei,
I. Vervoort,
H Bender,
M. Stucchi,
M. Schaekers,
W. Boullart,
M. Van Hove,
S. Vanhaelemeersch,
W. Peterson,
A. Shiota,
K. Maex
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ABSTRACT: The feasibility of integrating low-k spin-on dielectrics into a Cu damascene structure using JSR's LKD-5109 (k = 2.2) has been investigated. The chemical vapor deposited embedded etch-stop (ES) and dual hard-mask (HM) are replaced by JSR's spin-on dielectrics (organic FF-02 and MSQ type LKD-2022). In this study, the capability of FF-02 as an ES and as a chemical mechanical polishing (CMP) stop has been verified. In addition to electrical and mechanical film properties of FF-02, the chemical compatibility and removal rate to CMP slurries are investigated. Finally, the first successful single damascene (SD) integration with spin-on dual HM and ES is demonstrated and its electrical results including Raphael's model simulation of the k-value are reported.
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International; 02/2002
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ABSTRACT: In this article the dual damascene (DD) patterning has been examined for a full spin-on stack of a low-K material in K-value of 2.2 generation, i.e. LKD-5109 with dual low-K spin-on hard masks (SoHM). Compared to conventional CVD-deposited dual hard masks (dHM), the top spin-on HM has a wider range of thickness for which standing waves in the resist can be prevented. Furthermore, an etch selectivity has been obtained of more than 30 for LKD-5109 towards organic SoHM using fluorocarbon chemistries. Through the design of dHM structure and etch process development, it was possible to reduce the number of steps using an in-situ resist ash and organic SoHM strip during etching. A DD 0.2 μm trench/via structure was successfully etched.
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International; 02/2002
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ABSTRACT: Silicon-Oxy-Carbide (SiOC) materials are used as low-k materials for the 2.7-k generation. They can be etched with the fluorinated chemistries used for oxide but some optimizations are needed to achieve acceptable etch-rates and good selectivities. The resist strip is also very sensitive and requires even more development to keep the material properties intact after full damascene integration. Oxygen is useful but it can also cause severe damage. All experiments described in this paper were performed on Z3MS<sup>TM</sup> Low-k(*)
Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International; 02/2001
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S. Jenei,
S. Decoutere,
G. Winderickx, H. Struyf,
Z. Tokei,
I. Vervoort,
I. Vos,
P. Jaenen,
L. Carbonell,
B. De Jaeger,
R.A. Donaton,
S. Vanhaelemeersch,
K. Maex,
B. Nauwelaers
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ABSTRACT: Thick Cu single damascene inductors with very high Q factors are integrated on top of a standard aluminum 3LM BEOL process. Obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 2.8 nH inductance, a Q peak of 24 at 2 GHz was reached by using 4 μm thick Cu on a 2 μm IMD oxide layer.
Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International; 02/2001
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J.J. Waeterloos,
Shaffer,
E.O,
II,
Stokich,
J. Hetzner,
D. Price,
L. Booms,
R.A. Donaton,
G. Beyer,
B. Coenegrachts,
R. Caluwaerts, H. Struyf,
Z.S. Tokei,
I. Vervoort,
B. Sijmus,
I. Vos,
K. Maex,
T. Komiya,
M. Iwashita
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ABSTRACT: The feasibility of integrating a low permittivity spin-on hardmask (SoHM) into a Cu dual damascene structure using SiLK* Semiconductor Resin (*trademark of The Dow Chemical Company) has been investigated. The study focussed on the replacement of the embedded etch stop deposited by chemical vapor deposition (CVD) by a low permittivity inorganic film deposited by traditional spin coating. The evaluation was performed using an existing damascene test vehicle. The etch selectivity was evaluated by applying different SoHM thicknesses and etch times. The patterning chemistry used was O<sub>2</sub>/N<sub>2</sub> based, in a high density TCP etch tool. The electrical data collected indicated no significant yield difference when using an embedded SoHM. The integrated k value of the SoHM film is 3.2, as compared to ~4.0 for SiO<sub>2</sub> films
Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International; 02/2001
