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ABSTRACT: Design and performance of a 2:1 multiplexer and 1:2 demultiplexer IC up to 85.4 Gbit/s are presented. The chips are fabricated in an advanced SiGe technology with a cutoff frequency f/sub t/ of 200 GHz and a maximum oscillation frequency f/sub max/ of 275 GHz. With these two chips electrical data transmission at 80 and 85.4 Gbit/s could be achieved. In addition a pseudo random bit sequence (PRBS) generator IC is shown operating up to 80 Gbit/s and generating a 2/sup 31/-1 or a 2/sup 7/-1 pattern.
Gallium Arsenide and Other Semiconductor Application Symposium, 2005. EGAAS 2005. European; 11/2005
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Y. Baeyens,
N. Weimann,
P. Roux,
A. Leven,
V. Houtsma,
R.F. Kopf,
Yang Yang,
J. Frackoviak,
A. Tate,
J.S. Weiner, P. Paschke,
Young-Kai Chen
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ABSTRACT: High-performance and compact 40-Gb/s driver amplifiers were realized in 1.2-μm emitter double-heterojunction InGaAs-InP HBT (D-HBT) technology with a maximum cut-off frequency (f<sub>T</sub>) of 150 GHz and a maximum oscillation frequency (f<sub>max</sub>) of 200 GHz. Two-stage differential drivers feature a lumped input and fully distributed output stage and deliver a maximum differential output swing of 11.3 V peak-to-peak (V<sub>pp</sub>) at 40 Gb/s with less then 350 fs of added rms jitter and rise and fall times of about 7 ps while consuming a total power of 3 W. When biased at a lower output swing of 6.3 V<sub>pp</sub>, excellent 40-Gb/s eyes with a 7-ps fall time, 6-ps rise time, and no observable jitter deterioration compared with the input source are obtained at a reduced power consumption of 1.7 W. On-wafer measured differential S-parameters show a differential gain of 25 dB, 50 GHz bandwidth, and input and output reflection below -20 dB from 2 to 45 GHz. The amplifiers' small die size (1.0×1.7 mm), relatively low power consumption, large output swing, and ability to have dc coupled inputs and outputs enable compact 40-Gb/s optical transmitters with good eye opening for both conventional transmission formats such as nonreturn-to-zero and return-to-zero and alternative formats such as duobinary and differential phase shift keying.
IEEE Journal of Solid-State Circuits 11/2004; · 3.23 Impact Factor
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Y. Baeyens,
N. Weimann,
R. Kopf,
P. Roux,
V. Houtsma,
Y Yang,
A. Tate,
J. Frackoviak,
J. Weiner, P. Paschke,
Y.K. Chen
[show abstract]
[hide abstract]
ABSTRACT: A high-performance and compact 40 Gb/s driver amplifier was realized in a 1.2 μm emitter double-heterojunction InGaAs/InP HBT (D-HBT) technology. The 2-stage differential driver features a lumped input and fully distributed output stage and delivers more then 10 Vpp output swing at 40 Gb/s with 700 fs RMS jitter and rise and fall times of less than 8 ps. On-wafer measured S-parameters show a differential gain of 25 dB, more than 50 GHz bandwidth and in- and output reflection below -20 dB from 2-45 GHz. The amplifiers small die size (1.0×1.7 mm), relatively low power consumption and ability to have DC coupled in- and outputs, should enable compact 40 Gb/s transmitters with good 40 Gb/s optical eye opening for both NRZ, RZ, duobinary and DPSK transmission formats.
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003. 25th Annual Technical Digest 2003. IEEE; 12/2003
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ABSTRACT: Two broadband amplifiers for 43 Gbit/s data transmission were realized in a SiGe-HBT technology with f<sub>t</sub>=120 GHz and f<sub>max</sub>=100 GHz: a differential lumped limiting amplifier with 36 dB differential gain and 26 GHz bandwidth and a two stage distributed amplifier with a gain-bandwidth product of 820 GHz. Additionally, for applications beyond 43 Gbit/s, a distributed amplifier was realized in a more advanced SiGe process (f<sub>t</sub>, f<sub>max</sub> > 200 GHz). This amplifier achieves 13 dB gain and more than 80 GHz bandwidth, which is the highest bandwidth reported so far for Si-based amplifiers.
Microwave Conference, 2003. 33rd European; 11/2003
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ABSTRACT: Two broadband amplifiers for 43 Gbit/s data transmission were realized in a SiGe-HBT technology with ft = 120 GHz and fmax = 100 GHz: a differential lumped limiting amplifier with 36 dB differential gain and 26 GHz bandwidth and a two stage distributed amplifier with a gain-bandwidth product of 820 GHz. Additionally, for applications beyond 43 Gbit/s, a distributed amplifier was realized in a more advanced SiGe process (ft, fmax > 200 GHz). This amplifier achieves 13 dB gain and more than 80 GHz bandwidth, which is the highest bandwidth reported so far for Si-based amplifiers.
Microwave Conference, 2003. 33rd European; 11/2003
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J.S. Weiner,
A. Leven,
V. Houtsma,
Y. Baeyens,
Young-Kai Chen, P. Paschke,
Yang Yang,
J. Frackoviak,
Wei-Jer Sung,
A. Tate,
R. Reyes,
R.F. Kopf,
N.G. Weimann
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ABSTRACT: InP and SiGe technologies are both attractive for design of circuits operating at 40 GB/s and beyond. In this paper, we describe a fully differential SiGe transimpedance amplifier (TIA) suitable for differential phase-shift keying applications. The TIA exhibits 49 dB-Ω transimpedance, greater than 50-GHz bandwidth, and input-referred current noise less than 30 pA/√Hz. For comparison, we have also developed a similar TIA in an InP double-heterostructure bipolar transistor technology. The InP TIA had 48 dB-Ω transimpedance and 49-GHz bandwidth.
IEEE Journal of Solid-State Circuits 10/2003; · 3.23 Impact Factor
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ABSTRACT: High-performance and very compact 40 Gb/s driver amplifiers were realized in mature 0.15 μm depletion PHEMT technology. The 3-stage lumped differential drivers feature a large differential 40 Gb/s output swing of up to 7.5 V<sub>pp</sub>, RMS jitter of less than 800 fs, rise and fall times of less than 10 ps and more than 27 dB gain. The small size (1.4×1.7 mm) and ability to have DC coupled in- and output, enable compact and cost-effective optical 40 Gb/s long-haul transmitters with system grade NRZ and RZ eye diagrams.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE; 07/2003
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G. Georgiou,
Y. Baeyens,
Young-Kai Chen,
A.H. Gnauck,
C. Gropper, P. Paschke,
R. Pullela,
M. Reinhold,
C. Dorschky,
J.-P. Mattia,
T.W. von Mohrenfels,
C. Schulien
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ABSTRACT: The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.
IEEE Journal of Solid-State Circuits 10/2002; · 3.23 Impact Factor
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Y. Baeyens,
G. Georgiou,
J.S. Weiner,
A. Leven,
V. Houtsma, P. Paschke,
Q. Lee,
R.F. Kopf,
Yang Yang,
L. Chua,
C. Chen,
C.T. Liu,
Young-Kai Chen
[show abstract]
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ABSTRACT: The combination of device speed (f<sub>T</sub>, f<sub>max</sub> > 150 GHz) and breakdown voltage (V<sub>bceo</sub> > 8 V) makes the double heterojunction bipolar InP-based transistor (D-HBT) an attractive technology to implement the most demanding analog functions of 40-Gb/s transceivers. This is illustrated by the performance of a number of analog circuits realized in an InP D-HBT technology with an 1.2- or 1.6-μm-wide emitter finger: a low phase noise push-push voltage-controlled oscillator with -7-dBm output power at 146 GHz, a 40-GHz bandwidth and low-jitter 40-Gb/s limiting amplifier, a lumped 40-Gb/s limiting driver amplifier with 4.5-V<sub>pp</sub> differential output swing, a distributed 40-Gb/s driver amplifier with 6-V<sub>pp</sub> differential output swing, and a number of distributed preamplifiers with up to 1.3-THz gain-bandwidth product.
IEEE Journal of Solid-State Circuits 10/2002; · 3.23 Impact Factor
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Y.K. Chen,
Y. Baeyens,
C.-T. Liu,
R. Kopf,
C. Chen,
Y. Yang,
J. Frackoviak,
A. Tate,
A. Leven, P. Paschke,
M. Berger,
J. Weiner,
K. Tu,
G. Georgiou,
P. Roux,
V. Houstma,
U. Koc
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ABSTRACT: In this talk, we will examine how semiconductor IC technologies such as CMOS devices, ASICs, HEMTs, HBTs, will impact the performance of these functional blocks at 40 Gbps as well as the future prospective of utilizing these IC technologies to realize transceivers to transport data rate in the 100+ Gbps regime.
Optical Fiber Communication Conference and Exhibit, 2002. OFC 2002; 04/2002
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ABSTRACT: In this paper, we demonstrate a fully differential transimpedance amplifier (TIA) with 49 dB-ohm transimpedance, greater than 50 GHz bandwidth, and input-referred current noise less than 30pA/√(Hz).
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2002. 24th Annual Technical Digest; 02/2002
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ABSTRACT: A 40 Gb/s clock and data recovery (CDR) IC with 1:4 demultiplexer (DEMUX) is fabricated in a SiGe technology. The architecture provides robust operation combined with a high level of integration, dissipating 4.8 W from a 5.5 V supply
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International; 02/2001
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G Georgiou,
Y. Baeyens,
Y.K. Chen,
C. Groepper, P. Paschke,
R. Pullela,
M. Reinhold,
C. Dorschky,
J.P. Mattia,
T.W. von Mohrenfels,
C. Schulien
[show abstract]
[hide abstract]
ABSTRACT: The integrated clock data recovery (CDR) circuit is a key element for broad band optical communication systems at 40 Gb/s. We report a 40Gb/s CDR fabricated in Indium-Phosphide heterojunction bipolar transistor (InP HBT) technology using the more robust architecture of a phase lock loop with a digital early-late phase detector. The faster (compared to SiGe) InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This in turn reduces the circuit complexity (transistor count) and VCO requirements. The integrated IC includes an on-chip LC VCO and on-chip clock dividers to drive an external DEMUX and low frequency PLL control loop. On-chip limiting amplifier buffers are included for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed signal IC operating at the clock rate of 40 GHz. We describe the chip architecture and measurement results
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2001. 23rd Annual Technical Digest; 02/2001
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Y. Baeyens,
G Georgiou,
J. Weiner,
V. Houtsma, P. Paschke,
Q. Lee,
A. Leven,
R. Kopf,
J. Frackoviak,
C Chen,
C.T. Liu,
Y.K. Chen
[show abstract]
[hide abstract]
ABSTRACT: The combination of device speed (f<sub>T</sub>, f<sub>max</sub>>150 GHz) and breakdown voltage (V<sup>bcco</sup> of about 10 V), makes the double heterojunction InP-based HBT (D-HBT), a very attractive technology to implement the most demanding analog functions of 40 Gb/s transceivers. This is illustrated by the performance of a number of InP D-HBT circuits including millimeter-wave low phase-noise VCO's up to 146 GHz, low jitter 40 Gb/s limiting amplifiers, a 40 Gb/s driver amplifier with 4.5 V differential output swing and distributed pre-amplifiers with up to 1.4 THz gain-bandwidth
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2001. 23rd Annual Technical Digest; 02/2001
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Y.K. Chen,
Y. Baeyens,
C.-T. Liu,
R. Kopf,
R. Hamm,
C. Chen,
Y. Yang,
J. Frackoviak,
A. Tate, P. Paschke,
J. Weiner,
G. Georgiou,
P. Roux,
V. Houstma
[show abstract]
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ABSTRACT: For high speed TDM optical links, high speed physical layer
electronics provides critical interface between the local electronic
data traffic and high speed optoelectronic devices. We examine the
impact of several high speed compound semiconductor IC technologies such
as SiGe, GaAs, and InP, on the performance of optoelectronic
transceivers at data rate of 40 Gbps and 100+ Gbps regime. In this
paper, we utilize a 40 Gbps optoelectronics transceiver as an example to
illustrate the advantages and limitations of these compound
semiconductor IC technologies
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
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ABSTRACT: An InP HBT technology developed at Lucent Technologies Bell
laboratories, with peak f<sub>t</sub>-100 GHz is used to design and
fabricate a limiting amplifier with high gain and bandwidth margin at 10
Gbps. Feedback techniques are used to obtain >30 dB differential gain
with >10 GHz bandwidth for the packaged chip. The design reduces
current density with standard cell transistors to improve circuit
reliability (at the expense of performance). Stable operating conditions
are found by adjusting the DC bias tail currents. The limiting output is
set by the current in the output stage. Open eyes are obtained even with
>2 V differential output. Depending on the required output swing, the
power consumption is 200-500 mW (at V<sub>ee</sub>~-3.5 to -4.5 V)
Indium Phosphide and Related Materials, 1999. IPRM. 1999 Eleventh International Conference on; 02/1999
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ABSTRACT: Design and performance of a 2:1 multiplexer and 1:2 demultiplexer IC up to 85.4 Gbit/s are presented. The chips are fabricated in an advanced SiGe technology with a cutoff frequency ft of 200 GHz and a maximum oscillation frequency fmax of 275 GHz. With these two chips electrical data transmission at 80 and 85.4 Gbit/s could be achieved. In addition a pseudo random bit sequence (PRBS) generator IC is shown operating up to 80 Gbit/s and generating a 231-1 or a 27-1 pattern.
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ABSTRACT: Design and performance of a high speed 27-1 pseudo random bit sequence (PRBS) generator chip is presented. The circuit operates at a speed up to 86 Gbit/s and is fabricated in an advanced SiGe technology with a cutoff frequency ft of 200 GHz and a maximum oscillation frequency fmax of 240 GHz. It is based on a multiplexed linear feedback shift register and has a power consumption of 950 mW. An 1:2 demultiplexer, made in the same technology for up to 86 Gbit/s is also presented. With this two circuits electrical data transmission up 86 Gbit/s is demonstrated.
