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ABSTRACT: Voltage spikes are ubiquitous in biological nervous systems. How spikes can be used to encode signals, facilitate communication, and implement important computations is an important question of contemporary neuroscience. Acoustic processing tasks provide a rich range of applications for this encoding scheme. As a summary of the Ph.D. research of the first author, we present two analog VLSI spike-based example systems that process acoustic information using spikes: a model of the neural signal processing involved in bat echolocation, and a low-power, time-domain acoustic periodicity detector.
Biomedical Circuits and Systems Conference, 2008. BioCAS 2008. IEEE; 12/2008
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ABSTRACT: To support our ongoing work in modeling bat echolocation, an artificial bat head was designed and fabricated using a 3D printer, an ultrasonic cochlea-like filter bank with 16 channels was designed with moderate quality (Q) factor, and 128 spiking neurons convert these signals to spike trains. A two-dimensional address-event arbiter is used to transmit these spikes off of the chip. We demonstrate that the population of spiking neurons can be decoded to estimate azimuth and elevation of ultrasonic chirps. This chip was fabricated in a commercially- available 0.5 mum CMOS process and consumes approximately 36 muW.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
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ABSTRACT: We report a stochastic dynamical synapse for VLSI spiking neural systems. The compactness of the circuit, real-time stochastic behavior, and probability tuning make it well suitable to implement stochastic synapses with variety of dynamics. The stochastic synapse implements short-term depression (STD) using a subtractive single release model. Preliminary experimental results show a good match with theoretical predictions. The output from the stochastic synapse with STD has negative autocorrelation and lower power spectral density at low frequencies which can remove the information redundancy in the input spike train. The mean transmission probability is inversely proportional to the input spike rate which has been suggested as an automatic gain control mechanism in neural systems. The silicon stochastic synapse with plasticity could potentially be a powerful addition to existing deterministic VLSI spiking neural systems.
Biomedical Circuits and Systems Conference, 2007. BIOCAS 2007. IEEE; 12/2007
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ABSTRACT: The nature of the synaptic connection from the auditory nerve onto the cochlear nucleus neurons has a profound impact on how sound information is transmitted. Short-term synaptic plasticity, by dynamically modulating synaptic strength, filters information contained in the firing patterns. In the sound-localization circuits of the brain stem, the synapses of the timing pathway are characterized by strong short-term depression. We investigated the short-term synaptic plasticity of the inputs to the bird's cochlear nucleus angularis (NA), which encodes intensity information, by using chick embryonic brain slices and trains of electrical stimulation. These excitatory inputs expressed a mixture of short-term facilitation and depression, unlike those in the timing nuclei that only depressed. Facilitation and depression at NA synapses were balanced such that postsynaptic response amplitude was often maintained throughout the train at high firing rates (>100 Hz). The steady-state input rate relationship of the balanced synapses linearly conveyed rate information and therefore transmits intensity information encoded as a rate code in the nerve. A quantitative model of synaptic transmission could account for the plasticity by including facilitation of release (with a time constant of approximately 40 ms), and a two-step recovery from depression (with one slow time constant of approximately 8 s, and one fast time constant of approximately 20 ms). A simulation using the model fit to NA synapses and auditory nerve spike trains from recordings in vivo confirmed that these synapses can convey intensity information contained in natural train inputs.
Journal of Neurophysiology 05/2007; 97(4):2863-74. · 3.32 Impact Factor
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ABSTRACT: A compact true random number generator (RNG) integrated circuit with adjustable probability is presented. Hot-electron injection is used in a floating-gate MOSFET to program the probability. Measurements show no cross-correlation between adjacent RNG circuits, allowing multiple RNGs to be easily integrated
Electronics Letters 02/2006; · 0.96 Impact Factor
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T.K. Horiuchi
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ABSTRACT: While modern sonar and radar processing systems are constructed using large sensor arrays that have incredible imaging and localization capabilities, the question of what bats experience and how they process echo data with only two ears and a pea-sized brain remains a major mystery. The exploration of this question and the attempt to construct a functional model of the bat's neural signal processing using neuromorphic very large scale integration (VLSI) techniques and robotics have provided an interesting framework for our laboratory's research program.
IEEE Signal Processing Magazine 10/2005; · 4.07 Impact Factor
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ABSTRACT: The low-power, low-cost detection of voices or engine rumble is a desirable function in many different applications. Typical approaches involving frequency-domain computation are quite computationally intensive and require a significant power budget. In an effort to construct a very low-power detector capable of acting as a wake-up signal for other systems, we have designed a low-power (less than 1.8-μW) subthreshold analog very large-scale integration circuit that detects periodicity in the time-domain envelope of the acoustic signal. The circuit was fabricated in a commercially available 2-poly 1.5-μm CMOS process and occupies an area of about 0.242 mm<sup>2</sup>.
Circuits and Systems I: Regular Papers, IEEE Transactions on 10/2005; · 1.97 Impact Factor
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ABSTRACT: To support our ongoing work in modeling bat echolocation, a binaural, ultrasonic cochlea-like filter bank has been designed with moderate quality (Q) factor (as high as 65) with spiking neurons that are driven by the filter outputs. The neuron addresses are reported off chip at the time of the spike in an unarbitrated fashion and in current-mode to reduce the amount of capacitively-coupled feedback into the filters. This chip was fabricated in a commercially-available 0.5 μm CMOS process and consumes 0.425 milliwatts at 5 volts.
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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ABSTRACT: The dorsal nucleus of the lateral lemniscus (DNLL) is a distinct group of auditory cells that play a strategic role in azimuthal echolocation in the bat. Dominated by EI-type cells that receive excitation from the contralateral ear and inhibition from the ipsilateral ear, the DNLL processes interaural level difference (ILD) information by integrating inputs from lower brainstem areas and projecting its outputs to the midbrain. In this paper, we propose a two layer recurrent spiking neural network model that simulates ILD processing by the DNLL, and present a VLSI implementation using the address-event representation (AER) protocol. We demonstrate, using this neuromorphic VLSI-based hardware system, that long-lasting inhibition in the DNLL can alter its spatial selectivity to multiple sounds (objects).
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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ABSTRACT: Bats have long been the envy of engineers due to their ability to use echolocation to fly with speed and agility through complex 3D environments. By understanding the neurobiological basis for echolocation, we hope to emulate the efficient implementation demonstrated by nature. Bats use interaural level differences (ILD) as their primary cue for azimuthal echolocation. The Lateral Superior Olive (LSO) is the bats' first ILD processing center and plays an important role. We have designed a CMOS VLSI circuit based neuromorphic system that mimics ILD processing in the bat LSO. In this paper, we propose a simple spiking neural model of LSO cells, and a VLSI implementation of an array of cells representing the LSO population.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004
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ABSTRACT: Bats have long been the envy of engineers due to their ability to use echolocation to fly with speed and agility through complex 3D environments. By understanding the neurobiological basis for echolocation, we hope to emulate the efficient implementation demonstrated by nature. Bats use interaural level differences (ILD) as their primary cue for azimuthal echolocation. The Lateral Superior Olive (LSO) is bat's first ILD processing center and plays an important role. We have designed a CMOS VLSI circuit based neuromorphic system that mimics ILD processing in the bat LSO. In this paper,we propose a simple spiking neural model of LSO cells, and a VLSI implementation of an array of cells representing the LSO population.
04/2004;
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ABSTRACT: One way to understand a neurobiological system is by building a simulacrum that replicates its behavior in real time using similar constraints. Analog very large-scale integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a long-term effort to understand the primate oculomotor system. It requires both fast sensory processing and fast motor control to interact with the world. A one-dimensional hardware model of the primate eye has been built that simulates the physical dynamics of the biological system. It is driven by two different analog VLSI chips, one mimicking cortical visual processing for target selection and tracking and another modeling brain stem circuits that drive the eye muscles. Our oculomotor plant demonstrates both smooth pursuit movements, driven by a retinal velocity error signal, and saccadic eye movements, controlled by retinal position error, and can reproduce several behavioral, stimulation, lesion, and adaptation experiments performed on primates.
Neural Computation 02/1999; 11(1):243-65. · 1.88 Impact Factor
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ABSTRACT: An object-based analog very large-scale integration (VLSI) model
of selective attentional processing has been implemented using a
standard 2.0-μm CMOS process. This chip extends previous work on
modeling a saliency-map-based selection and scanning mechanism to
incorporate the ability to group pixels into objects. This grouping, or
segmentation, couples the circuitry of the object's pixels to act as a
single, larger pixel. The grouping of pixels is dynamic, driven solely
by the segmentation criterion at the input. In this demonstration
circuit, image intensity has been chosen for the input saliency map and
the segmentation is based on spatial low-pass filtering followed by an
intensity threshold. We present experimental results from a
one-dimensional implementation of the object-based analog VLSI
selective-attention system
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 01/1999;
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ABSTRACT: Using the analog VLSI-based saccadic eye movement system
previously developed we investigate the use of biologically realistic
error signals to calibrate the system in a manner similar to the primate
oculomotor system. In this paper we introduce two new circuit components
which are used to perform this task, a resettable-integrator model of
the burst generator with a floating-gate structure to provide on-chip
storage of analog parameters and a directionally-selective motion
detector for detecting post-saccadic drift
Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on; 03/1996
