F. Ellinger

Technische Universität Dresden, Dresden, Saxony, Germany

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Publications (211)160.08 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power (LP) bulk CMOS process. As the technology is optimized for digital LP applications, the design of millimeter-wave (mm-wave) circuits requires high-frequency design and modeling of all active and passive devices. This includes the development of a suitable RF-transistor layout, as well as transmission lines and high- capacitors. The mm-wave circuit design aspects are further discussed with considerations about possible dc-distribution approaches, broadband matching networks, and optimum transistor loads. The proposed approach and device models have been validated with the fabrication and characterization of a two-stage 60-GHz LNA. This circuit exhibits 13.8 dB of power gain, 18 GHz of bandwidth, 4 dB of minimum noise figure, and an input referred 1-dB compression point at 12.5 dBm consuming 24 mW of dc power. Based on this performance and to the authors’ best knowledge, the presented amplifier shows the highest reported value for a commonly used figure-of-merit of 60-GHz LNAs.
    IEEE Transactions on Microwave Theory and Techniques 06/2015; 63(6):1-13. DOI:10.1109/TMTT.2015.2427794 · 2.94 Impact Factor
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    ABSTRACT: This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28 nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406 mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.
    RFIC 2015; 05/2015
  • J. Wagner, F. Ellinger, N. Joram, R. Wolf
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    ABSTRACT: An inductorless vector modulator-based radio frequency (RF) weighting circuit working from 1 to 10 GHz is presented. Amplitude and phase interdependencies were strongly reduced employing optimised attenuators. The vector modulator features a 360° phase and more than 40 dB amplitude control range with a root mean square phase and amplitude error of only 6° and 0.16 dB, respectively. These features make it a suitable candidate for communication and localisation diversity frontends in the 2.4 and the 5.9 GHz industrial, scientific and medical (ISM) bands. The circuit was fabricated in a 180 nm BiCMOS technology and contains an inter-integrated circuit (I2C) control interface and digital-to-analogue converters. It consumes 87 mW and requires an area of only ≃0.2 mm2.
    Electronics Letters 05/2015; 51(10). DOI:10.1049/el.2015.0343 · 1.07 Impact Factor
  • IET Circuits Devices & Systems 05/2015; 9(3). DOI:10.1049/iet-cds.2014.0240 · 0.91 Impact Factor
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    ABSTRACT: The design, analysis, modelling and measurement of transmission lines with very low characteristic impedance in 28 nm bulk CMOS is presented. The so-called zero-Ohm lines are very well suited for power distribution networks and AC shorts in millimetre-wave circuits because of their accurate modelling up to extremely high frequencies and because they do not require metal–insulator–metal capacitors, which are usually not available in digital CMOS processes. Instead, they rely on simple metal structures, which can optionally be enhanced by integrating MOS capacitors. Applying transmission line theory, the lines can be described with models, which are scalable in length and width. Implemented test structures demonstrate a compact line of 450 μm length, which transforms an open circuit to an impedance close to 0 Ω for frequencies above 1 GHz.
    Electronics Letters 05/2015; 51(11). DOI:10.1049/el.2015.0903 · 1.07 Impact Factor
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    ABSTRACT: The design and electro-optical measurements of a 25 Gbit/s common cathode vertical cavity surface-emitting laser (VCSEL) driver in 90 nm bulk CMOS technology is presented. The driver is bonded to a 14 Gbit/s commercial VCSEL providing both DC and modulation current to the laser. The power consumption including the VCSEL is 60 mW. Since the DC bias of the VCSEL exceeds the breakdown voltage of thin oxide transistors, a novel output stage configuration using isolated wells is proposed. The active area is only 127 × 50 μm.
    Electronics Letters 02/2015; 51(4). DOI:10.1049/el.2014.4217 · 1.07 Impact Factor
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    ABSTRACT: It is well known that there are many limitations of the current positioning systems either indoors or outdoors. Moreover, most of the current positioning systems require preinstalled infrastructure in the surrounding environment, which is costly in most cases and requires special devices from the user side. The near field communications (NFC), inertial sensors, pressure sensor for height, magnetometers for heading are built in sensors in most modern smart devices. Therefore, they can be used as a low-cost platform for gathering and processing location information. The main target of this work is to reduce the needed infrastructure as much as possible and maximize the use of the components that are built-in or can be connected to the smart devices. The accurate solution which we propose combines the NFC with an inertial navigation system (INS). The advantage of the inertial sensors based approach is that it does not need a preinstalled infrastructure and it starts on basis of a reference location given by the other positioning methods. The NFC approach can work based on simple sensors located in smart shoes that interacts with non-expensive NFC tags preinstalled at the desired floor of the building. Experimental results show that the combination can keep accurate positioning of a pedestrian and limit the error growth of inertial sensors using properly distributed NFC tags. The maximum error in NFC/INS pedestrian dead reckoning (PDR) position is below 1.7 m in the whole track using direct position resetting approach.
    International Symposium on Fundamentals of Electrical Engineering 2014, Romania; 11/2014
  • IET Circuits Devices & Systems 11/2014; 8(6):459-468. DOI:10.1049/iet-cds.2013.0333 · 0.91 Impact Factor
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    ABSTRACT: Monitoring of constructed facilities, critical or not, utilised by different organisations or by the public in general and in particular during natural or manmade disasters, tends to be of paramount importance, as these structures are instantly becoming of keen interest to a variety of authorities. This paper presents the work that is currently being performed in the RECONASS project [1], towards providing a monitoring system to assess the structural condition and related needs of single or grouped facilities. This system encompasses technologies originating from different domains that are seamlessly interworking with the aim to shorten the required time of assessments and to establish an efficient updating process. The overall technology to be implemented in RECONASS is focusing on the case of reinforced concrete buildings that constitute the main type of construction of critical buildings in the earthquake prone countries of Europe, as well as, the rest of Europe and North America. The RECONASS system proposes the following synergistic approach: a compact and highly energy efficient local positioning system (LPS) cooperating with a set of strategically placed strain, acceleration and temperature sensors and the aggregation of sensor information through a robust, secure, intelligent and resilient communication module. Additionally, a remote sensing approach complements the aforementioned methodology, using air borne and space borne systems. Last but not least, the data fusion and the overall structural assessment will be enabled within an interoperable Post Crisis Needs Assessment Tool in regards to Construction Damage and related Needs (PCCDN) which will be a platform that includes both an assessment and an economic loss and needs module.
    2014 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems - 2014 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems, Naples, Italy; 09/2014
  • B. Al-Qudsi, E. Edwan, N. Joram, F. Ellinger
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    ABSTRACT: The aim of this research paper is to explore the feasibility of integrating an inertial measurement unit (IMU) with a frequency-modulated continuous wave (FMCW)-based local positioning system (LPS) to mitigate the effects of multipath bias in highly reflective indoor scenarios. The LPS uses a time difference of arrival (TDOA) positioning scheme. The IMU consists of accelerometer and gyroscope triads. Using a proper integration algorithm combined with a zero-velocity update (ZUPT) technique, a mitigation of about 40% is achieved in terms of the overall LPS position absolute error.
    Inertial Sensors and Systems – Symposium Gyro Technology 2014, Karlsruhe; 09/2014
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    ABSTRACT: This paper presents the design and characterization of a 220–240 GHz four-element Butler matrix beam switching chip. It is realized in 0.13 µm SiGe BiCMOS technology. The chip features four 220 GHz amplifiers with 9 dB of gain followed by the Butler matrix core. A single-pole-four-throw (SP4T) switch is integrated to switch between the different beam directions. Finally an amplifier is used to compensate the losses of the matrix core and the switch. The chip exhibits a 2 dB of insertion loss and draws 104 mA from a 3.3 V supply. It also shows maximum phase error of 15° from the ideal phase states and less than 4 dB rms amplitude variations. The chip occupies 1.5 × 2.4 mm 2 silicon area.
    IEEE Journal of Solid-State Circuits 09/2014; 49(9):1916-1926. DOI:10.1109/JSSC.2014.2317147 · 3.11 Impact Factor
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    ABSTRACT: A novel fully printed 28-bits capacity chipless RFID tag using conical resonators is proposed here. The angle of aperture of these resonators is adjusted to suppress high order modes allowing an efficient use of the UWB frequency bandwidth. By using 12 resonators within a reduced dimension of 4.2 × 3 cm 2 , a coding capacity of 28 bits is achieved, which is the highest coding capacity reported for a fully printed chipless tag. Several chipless tags are printed on flexible substrate and validated experimentally.
    Progress In Electromagnetics Research Symposium, Guangzhou, China; 08/2014
  • Weiran Cai, Frank Ellinger, Ronald Tetzlaff
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    ABSTRACT: We propose a new memristive model for the neuronal synapse based on the spike-timing-dependent plasticity (STDP) protocol, considering both long-term and short-term plasticity in the synapse. Higher-order behavior is modeled by a memristor with adaptive thresholds, which realizes the well-established suppression principle of Froemke. We assume a mechanism of variable thresholds adapting to synaptic potentiation (LTP) and depression (LTD), which reproduces the refractory time in the weight modification. The corresponding dynamical process is governed by a set of ordinary differential equations. Interestingly, the Froemke's model and our memristive model, based on two completely different mechanisms, are found to be quantitatively equivalent for the 'pre-post-pre' case and 'post-pre-post' case. A relation of the adaptive thresholds to short-term plasticity is addressed.
    IEEE Transactions on Biomedical Circuits and Systems 06/2014; 9(1). DOI:10.1109/TBCAS.2014.2318012 · 3.15 Impact Factor
  • Microwaves, Radar, and Wireless Communication (MIKON), 2014 20th International Conference on; 06/2014
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    ABSTRACT: The design methodology of low power current mode logic (CML) latches is described and the implementation of a D flip-flop (DFF) is presented in 28 nm CMOS technology. The DFF can work up to 22 Gbps full-rate with a bit error rate better than 10-12 and with a power consumption of only 880 μW. Since the circuit is inductor-less the area of the circuit is only 25 μm × 10 μm. As a further implementation of the CML latches a very low power static frequency divider with quadrature outputs in 28 nm is presented. It divides the clock signal up to 26 GHz and has only 880 μW power consumption. To our knowledge, with 0.034 mW/GHz, this static frequency divider has one of the best figure of merit reported to date.
    2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME); 06/2014
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    ABSTRACT: An enhancement of an analytical algorithm to simplify and structure the design of stacked power amplifiers is presented in this work. This enhancement includes the calculation of passive networks, which compensate the parasitic capacitances of the transistors and thereby increase the distortion-free output power and the power added efficiency (PAE). As an example the algorithm is applied to a power amplifier (PA), using the IBM 180 nm CMOS process. The PA operates at 2GHz for the long term evolution (LTE) standard. The post-layout-simulation exhibits an output power in the 1 dB compression point of 28.2 dBm, leading to a PAE of 30%. The relative 3 dB bandwidth of the output power reaches a high value of 33%. The PA fulfills the specifications of LTE and therewith the high requirements on linearity.
    2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME); 06/2014
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    ABSTRACT: This article presents a fractional-N phase-locked loop (PLL) for the use in frequency-modulated continuous wave (FMCW) radar systems. The presented design supports division ratios from 59 to 4092 with a maximum input frequency of 7GHz, covering the 2.39GHz to 3.28GHz and 4.79GHz to 6.55GHz bands using a dual-band voltage-controlled oscillator (VCO) with a frequency resolution of 0.6Hz. This corresponds to a large relative bandwidth of more than 31%. Reference spur levels are lower than -65 dBc while phase noise is at -103 dBc/Hz at 1MHz offset frequency. A key feature for radar applications is the automatic chirp waveform generation. The complete circuit including VCO consumes less than 122mW and is implemented using an IBM 180 nm SiGe BiCMOS process.
    2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME); 06/2014
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    ABSTRACT: Fully printed organic field effect transistors (OFETs) are fabricated on a flexible, 100- $mu{rm m}$ -thick, polyethylene terephthalate substrate using high-throughput printing techniques: 1) Cyflex; 2) gravure; 3) screen; and 4) flexographic printing without using a cleanroom, and below 130 $^{circ}{rm C}$ . The dependence of the transconductance $({g}_{m})$ , transit-frequency $({f}_{T})$ , and intrinsic-gain on the bias drain current $({I}_{rm D})$ are measured. The OFETs show intrinsic gain for ${I}_{rm D}>10~{rm nA}/{rm mm}$ (per millimeter width), and reach ${f}_{T}=64~{rm kHz}$ at ${I}_{rm D}=16~mu{rm A}/{rm mm}$ , whereas the ${g}_{m}$ loss with frequency is ${<}{10%}$ up to ${f}_{T}$ . Unlike silicon MOSFETs, the dependence of the OFET ${g}_{m}$ on the ${f}_{T}$ in the subthreshold region is found to be weaker than ${I}_{rm D}^{1.0^{vphantom{)}}}$ . In addition, the overlap capacitance of the staggered-geometry OFET shows strong frequency dependence, and this is - hown to be related to the overlap semiconductor. For the first time, it is found that the impact of process variations and bias stress on the OFET analog characteristics can be significantly attenuated by biasing the device at a fixed ${I}_{rm D}$ . This approach is tested on an array of five amplifiers, reaching the gain-bandwidth product of 32 kHz, within ${pm}{3.7%}$ variations.
    IEEE Transactions on Electron Devices 05/2014; 61(5):1423-1430. DOI:10.1109/TED.2014.2315038 · 2.36 Impact Factor
  • N. Joram, R. Wolf, F. Ellinger
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    ABSTRACT: A compensated charge pump for use in phase-locked loops (PLLs) is presented, which reaches several of the desired design goals for this type of circuit. The measured mismatch between the source and sink currents is below 2.1% for a large output voltage headroom of 83.3% of the supply, while still having a high output resistance of 140 k Omega. This behaviour is reached with a novel dual compensation method. The circuit was implemented in a 180 nm CMOS technology using a 3 V supply.
    Electronics Letters 04/2014; 50(9):661-663. DOI:10.1049/el.2014.0804 · 1.07 Impact Factor
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    ABSTRACT: In this paper a 3 bit chipless RFID tag able to be printed using mass production techniques is introduced. The structure proposed is based on dipole like structures and three of such dipoles conforms a tag. Several chipless RFID tag prototypes were fabricated on PET substrate and measured within the frequency band from 2 GHz to 5 GHz. In contrast to the already reported printed tags where inkjet printing is used, the proposed tag is fabricated using screen printing techniques which enable fast mass production of tags in a very short time with thick conductive tracks of ~10 μm. A good agreement between simulation and measurement was obtained and a reading distance up to 1 m is obtained with a transmission power of 3 dBm. The obtained results confirm the use of low cost printed tags for mass market applications.
    The European Association on Antennas and Propagation EUCAP 2014, The Hague; 04/2014

Publication Stats

2k Citations
160.08 Total Impact Points


  • 2007–2014
    • Technische Universität Dresden
      • Institut für Angewandte Photophysik
      Dresden, Saxony, Germany
  • 2005–2010
    • ETH Zurich
      • Electronics Laboratory
      Zürich, ZH, Switzerland
  • 2009
    • Siemens
      München, Bavaria, Germany
  • 2005–2006
    • IBM
      Armonk, New York, United States
  • 1999–2001
    • Eawag: Das Wasserforschungs-Institut des ETH-Bereichs
      Duebendorf, Zurich, Switzerland