F. Ellinger

Technische Universität Dresden, Dresden, Saxony, Germany

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Publications (238)165.08 Total impact

  • R. Henker · F. Ellinger · D. Schoeniger ·

    Electronics Letters 11/2015; DOI:10.1049/el.2015.3123 · 0.93 Impact Factor
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    ABSTRACT: This paper presents two high-gain amplifiers fabricated in a flexible self-aligned amorphous indium gallium zinc oxide thin-film transistor (TFT) technology. One common-source amplifier relies on positive feedback to provide a voltage gain of 17 dB, and a bandwidth of 79 kHz from a dc power of only 0.76 mW. One cascode amplifier provides a voltage gain of 25 dB, and a bandwidth of 220 kHz from a dc power of 2.32 mW. The chip areas of the amplifiers are 7.5 and 10.3 mm2, respectively. By using a gain-enhancement technique in the first amplifier, gain, dc power consumption, and chip area are greatly improved. The presented amplifiers are designed for using as audio pre-amplifiers in a radio receiver. The presented measurements confirm that the amplifiers meet the requirements for this purpose. The circuits are designed using the Verilog-A Rensselaer Polytechnic Institute-amorphous TFT model; circuit simulations are also presented for comparison with the hardware characterization. Additionally, the impact of process variations on the amplifiers is analyzed and discussed in details.
    Analog Integrated Circuits and Signal Processing 10/2015; DOI:10.1007/s10470-015-0655-3 · 0.47 Impact Factor
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    ABSTRACT: An optimized vertical organic permeable-base transistor (OPBT) competing with the best organic field-effect transistors in performance, while employing low-cost fabrication techniques, is presented. The OPBT stands out by an excellent power efficiency at the highest frequencies.
    Advanced Materials 10/2015; DOI:10.1002/adma.201502788 · 17.49 Impact Factor
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    ABSTRACT: This paper presents a travelling-wave amplifier (TWA) for wideband applications implemented in a 0.13 m SiGe BiCMOS technology ( 300 GHz, 500 GHz). The gain cell employed in the TWA is designed to compensate the synthetic-line losses at high frequencies in order to extend the bandwidth as well as the gain bandwidth product (GBP). A gain of 10 dB and a 3 dB bandwidth of 170 GHz are measured for the fabricated circuit. The circuit analysis is presented to illustrate how the bandwidth of the circuit is dominated by the cutoff frequency of the synthetic lines, thus demonstrating complete losses compensation for the band of interest. The chip required a total area of 0.38 mm and a power consumption of 108 mW. Compared against the state of the art, the presented design achieves the highest reported GBP per power consumption and area, as well as the highest operation frequency for silicon implementations.
    IEEE Journal of Solid-State Circuits 10/2015; 50(10):1-11. DOI:10.1109/JSSC.2015.2444878 · 3.01 Impact Factor
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    ABSTRACT: This letter presents an active 200 GHz fundamental down-conversion mixer based on the Micromixer topology for low-power high data-rate wireless communications. The mixer-core operation requires a 5 dBm LO-signal, which is generated on-chip from an external single-ended source of only 20 dBm by means of a power-efficient LO-driver and a passive balun. Mixer, LO-driver and balun have been implemented together in a 450 GHz SiGe BiCMOS technology occupying a circuit core area of 0.21 mm . For a 200 GHz LO-signal, the characterized circuit exhibits a maximum conversion gain of 5.5 dB over a 3 dB RF-bandwidth of 30 GHz, requiring only 17.4 and 22.5 mW of DC-power in the mixer core and in the LO-driver, respectively.
    IEEE Microwave and Wireless Components Letters 09/2015; 25(9):594-596. DOI:10.1109/LMWC.2015.2451353 · 1.70 Impact Factor
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    ABSTRACT: Fully mass printed, flexible and truly polymeric organic field effect transistors consisting of a three layer dielectric made of CYTOP (low-k), PVA (intermediate) and P(VDF-TrFE-CTFE)(high-k) are introduced. Gravure-, flexo-and screen printing were selected as highly productive manufacturing technologies. These OFETs work at strongly reduced voltages and show high field effect mobility (μ-=-0.2-cm2/Vs) and remarkable good bias stress stability at very high current density (50-μA/mm). Fully printed OFETs are used for the realization of ring oscillators working in the kHz regime at reduced supply voltage (10-V). In combination with printed fully polymeric piezoelectric loudspeakers, this work shows for the first time fully printed flexible audio systems.
    Journal of Polymer Science Part B Polymer Physics 07/2015; 53(20). DOI:10.1002/polb.23778 · 3.83 Impact Factor
  • R. Paulo · P.V. Testa · C. Tzschoppe · J. Wagner · F. Ellinger ·
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    ABSTRACT: In this paper, we discuss layout problems encountered in power amplifiers with negative parallel feedback. We show how to reduce the risk of an unstable power amplifier (PA) by careful layouting without the use of additional elements and thus chip area. Optimised vs. non-optimised layouting are compared and verified with fabricated ICs. Finally a PA with large signal bandwidth of 1.9 GHz at a design frequency of 2.6 GHz using negative feedback in a standard 250 nm BiCMOS technology is introduced. An efficiency of 34% and an output power of 26.9dBm at the 1 dB compression point were measured.
  • M. Schulz · N. Joram · F. Ellinger ·
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    ABSTRACT: In this publication, a fully integrated active backscatter transponder for the positioning and fast rescue of passengers from sea in case of a ship sinking emergency is presented. The active reflector tag is applied in a frequency modulated continuous wave (FMCW) radar and to the authors knowledge is for the first time ever reported based on a Colpitts oscillator topology in common-base configuration. The circuit is operated as a switched injection-locked oscillator (SILO). Furthermore, measurements regarding a self-locking phenomenon to the modulation signal are carried out. The presented backscatter tag operates at 2.45 GHz and reaches a steady-state output power of 12.3 dBm for on PCB measurements.
  • P.V. Testa · C. Carta · F. Ellinger ·
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    ABSTRACT: This paper presents a four-stage cascaded single-stage distributed amplifier (CSSDA) for wideband and low power applications implemented in a 0.13 μm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). A 3 dB upper frequency of 180 GHz, a bandwidth of 130 GHz, and a gain of 9.5 dB are measured for the fabricated CSSDA. The circuit requires a chip area of 0.28 mm2 and only 19.5 mW of dc power consumption. To enhance the amplifier gain and bandwidth without increasing the dissipated power, innovative peaking techniques have been employed. Compared against the state of the art, the presented design solution offers the lowest power consumption and the smallest occupied area, without sacrificing excessively speed, gain and gain-bandwidth product.
  • David Fritsche · Gregor Tretter · Corrado Carta · Frank Ellinger ·
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    ABSTRACT: This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power (LP) bulk CMOS process. As the technology is optimized for digital LP applications, the design of millimeter-wave (mm-wave) circuits requires high-frequency design and modeling of all active and passive devices. This includes the development of a suitable RF-transistor layout, as well as transmission lines and high- capacitors. The mm-wave circuit design aspects are further discussed with considerations about possible dc-distribution approaches, broadband matching networks, and optimum transistor loads. The proposed approach and device models have been validated with the fabrication and characterization of a two-stage 60-GHz LNA. This circuit exhibits 13.8 dB of power gain, 18 GHz of bandwidth, 4 dB of minimum noise figure, and an input referred 1-dB compression point at 12.5 dBm consuming 24 mW of dc power. Based on this performance and to the authors’ best knowledge, the presented amplifier shows the highest reported value for a commonly used figure-of-merit of 60-GHz LNAs.
    IEEE Transactions on Microwave Theory and Techniques 06/2015; 63(6):1-13. DOI:10.1109/TMTT.2015.2427794 · 2.24 Impact Factor
  • L. Szilágyi · G. Belfiore · R. Henker · F. Ellinger ·
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    ABSTRACT: An 18Gbps optical receiver in 80nm CMOS with a limiting amplifier employing offset compensation and common-mode control is implemented. A conventional and a proposed, 40% smaller circuit in switched-capacitor technique are measured and compared.
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    ABSTRACT: This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28 nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406 mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.
    RFIC 2015; 05/2015
  • J. Wagner · F. Ellinger · N. Joram · R. Wolf ·
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    ABSTRACT: An inductorless vector modulator-based radio frequency (RF) weighting circuit working from 1 to 10 GHz is presented. Amplitude and phase interdependencies were strongly reduced employing optimised attenuators. The vector modulator features a 360° phase and more than 40 dB amplitude control range with a root mean square phase and amplitude error of only 6° and 0.16 dB, respectively. These features make it a suitable candidate for communication and localisation diversity frontends in the 2.4 and the 5.9 GHz industrial, scientific and medical (ISM) bands. The circuit was fabricated in a 180 nm BiCMOS technology and contains an inter-integrated circuit (I2C) control interface and digital-to-analogue converters. It consumes 87 mW and requires an area of only ≃0.2 mm2.
    Electronics Letters 05/2015; 51(10). DOI:10.1049/el.2015.0343 · 0.93 Impact Factor
  • Jan Dirk Leufker · Corrado Carta · Frank Ellinger ·
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    ABSTRACT: This paper presents a 60 GHz differential single-stage power amplifier IC with extrapolated 24.5 dBm output power and 12.9 % power added efficiency at 1 dB compression. The circuit is based on distributed amplification with four parallel cascode stages and power combination with a transformer. It shows a 3 dB gain bandwidth of 12 GHz from 51 GHz to 63 GHz with maximum power gain of 12.3 dB at 58 GHz. It consumes 600 mA from a 3.3 V supply and was fabricated in a 250 nm SiGe BiCMOS technology with peak fT and fmax of 180 GHz and 220 GHz, respectively. The high linearity of the circuit exceeds the capabilities of the available measurement instrumentation. A maximum output power of 16.5 dBm has been observed; extrapolation from the measured data and matching simulated performance allow predicting an output power of 24.5 dBm at 1 dB compression. This value, to the best knowledge of the authors, would be the highest reported to date for 60 GHz silicon power amplifiers.
  • M. El-Shennawy · N. Joram · F. Ellinger ·
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    ABSTRACT: This work addresses the optimization of Fractional-N Phase Locked Loops (Frac-N PLLs) used to produce frequency chirps for Frequency Modulated Continuous Wave (FMCW) radar applications. In a Frac-N PLL, we have two main clock domains which are the reference and the divided clock domains. Clock domain crossings have to be considered during chirp generation to produce highly linear chirps. Moreover, with wideband chirps, integer divide ratio increments during chirp generation may cause transient frequency glitches which also affect the chirp linearity if not taken care of. In this work we propose techniques to address these issues in Frac-N PLLs. The proposed techniques lead to highly linear wideband chirp generation and thus improve the distance calculation accuracy by a factor of 2 and the distance calculation precision by a factor of 1.5.
  • D. Fritsche · G. Tretter · C. Carta · J.D. Leufker · F. Ellinger ·
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    ABSTRACT: The design, analysis, modelling and measurement of transmission lines with very low characteristic impedance in 28 nm bulk CMOS is presented. The so-called zero-Ohm lines are very well suited for power distribution networks and AC shorts in millimetre-wave circuits because of their accurate modelling up to extremely high frequencies and because they do not require metal–insulator–metal capacitors, which are usually not available in digital CMOS processes. Instead, they rely on simple metal structures, which can optionally be enhanced by integrating MOS capacitors. Applying transmission line theory, the lines can be described with models, which are scalable in length and width. Implemented test structures demonstrate a compact line of 450 μm length, which transforms an open circuit to an impedance close to 0 Ω for frequencies above 1 GHz.
    Electronics Letters 05/2015; 51(11). DOI:10.1049/el.2015.0903 · 0.93 Impact Factor
  • Udo Jörges · Frank Ellinger · Laszlo Szilagyi · Ronny Henker · Guido Belfiore ·
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    ABSTRACT: This paper presents the design and analysis of a 4-level pulse-amplitude-modulation (4-PAM) 56 Gbit/s vertical-cavity surface-emitting laser (VCSEL) driver integrated circuit (IC) for short range, high speed and low power optical interconnections. An amplitude modulated signal is necessary to overcome the bottleneck of speed given by the actual VCSELs and decrease the power consumption per bit. A prototype IC is developed in a standard 130 nm BiCMOS technology. The circuit converts two single-ended input signals to a 4-level signal fed to the laser. The driver also provides the DC current and the voltage necessary to bias the VCSEL. The power dissipation of the driver is only 115 mW including both the VCSEL and the 50 Ω input single-to-differential-ended converters. To the author's knowledge this is the first 56 Gbit/s 4-PAM laser driver implemented in silicon with a power dissipation per data-rate (DR) of 2.05 mW/Gbit/s including the VCSEL making it the most power efficient, 56 Gbit/s, common cathode laser driver. The active area occupies 0.056 mm2. The small signal bandwidths are 49 GHz for the high and 43 GHz for the low amplitude amplification path, when the VCSEL is not connected. The bit error rate was tested electrically showing and error free connection at 28 GBaud/s.
    IET Circuits Devices & Systems 05/2015; 9(3). DOI:10.1049/iet-cds.2014.0240 · 0.52 Impact Factor
  • Source
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    ABSTRACT: To our knowledge, this paper presents the first high-gain amplifiers fabricated in flexible self-aligned amorphous indium gallium zinc oxide (a-IGZO) thin-film-transistor (TFT) technology. For the common source amplifier applying positive feedback a voltage gain of 17 dB, a bandwidth of 79 kHz and a DC power of only 0.76 mW were measured. For the cascode amplifier a voltage gain of 25 dB voltage gain, a bandwidth of 220 kHz and a DC power of 2.32 mW were measured. The simulations based on a RPI-aTFT model are compared with measurements. The chip areas are 8 and 10 mm2, respectively.
  • C. Tzschoppe · R. Wolf · D. Fritsche · A. Richter · F. Ellinger ·
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    ABSTRACT: In this paper, a fully integrated Doherty power amplifier (DPA) for application in IEEE 802.11a wireless local area network (WLAN) transmitters is proposed. The DPA exhibits an output power at its 1 dB compression point of 22 dBm with a corresponding power added efficieny (PAE) of 25 %. Within a 6dB-backoff the PAE is still 20 %, which among the highest reported for Doherty amplifiers fully integrated in silicon. The input reflection coefficient is less than -15 dB while the maximum forward transmission is 12.5 dB. This Doherty amplifier shows a low phase variation of only 16° over an input dynamic range of 30 dB. To verify the performance the DPA is measured with an orthogonal frequency divison multiplexed (OFDM) signal with 52 carriers using 16 QAM modulation scheme and a carrier frequency of 5.6 GHz. Error vector magnitudes are measured for different input power levels. The circuit is implemented in IHP 250nm-SiGe-BiCMOS technology and needs a 2.5 V supply. The chip area is 1.54 mm2 × 0.85 mm2 including the pads and eleven integrated inductors.
  • A. Richter · C. Tzschoppe · F. Ellinger ·
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    ABSTRACT: A low power Fast Ethernet line driver has been designed in a 180 nm CMOS technology from XFAB. A very low power consumption is achieved with class-B operation. Due to incorporating digital-to-analog conversion to the line driver itself, the power consumption could be further reduced. The power consumption in transmit mode is minimized to 38 mW, which is the lowest one of previous reported line drivers fabricated in a comparable technology.

Publication Stats

2k Citations
165.08 Total Impact Points


  • 2007-2015
    • Technische Universität Dresden
      • Institut für Angewandte Photophysik
      Dresden, Saxony, Germany
  • 2009
    • Siemens
      München, Bavaria, Germany
  • 2005-2006
    • IBM
      Armonk, New York, United States
  • 2003-2004
    • ETH Zurich
      • Electronics Laboratory
      Zürich, Zurich, Switzerland
  • 1999-2001
    • Eawag: Das Wasserforschungs-Institut des ETH-Bereichs
      Duebendorf, Zurich, Switzerland