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[show abstract]
[hide abstract]
ABSTRACT: Reduction of threading dislocation density is critical for improving the performance of HgCdTe detectors on lattice-mismatched
alternative substrates such as Si. CdTe buffer layers grown by molecular beam epitaxy (MBE), with thicknesses on the order
of 8μm to 12μm, have helped reduce dislocation densities in HgCdTe layers. In this study, the reduction of threading dislocation densities
in CdTe buffer layers grown on locally thinned Si substrates was examined. A novel Si back-thinning technique was developed
that maintained an epiready front surface and achieved Si thicknesses as low as 1.9μm. Threading dislocation densities, acquired by defect decoration techniques, were reduced by as much as 60% for CdTe buffer
layers grown on these thinned regions when compared with unthinned regions. However, this reduction is inconsistent with prior
notions that threading dislocation propagation is dominated by image forces. Instead, the thickness gradient of thinned Si
may play a larger role.
KeywordsHgCdTe–CdTe–Silicon–compliant substrate–wafer thinning–threading dislocation–mismatched heteroepitaxy
Journal of Electronic Materials 04/2012; 40(8):1809-1814. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: Large-area high-quality Hg1–x
Cd
x
Te sensing layers for infrared imaging in the 8μm to 12μm spectral region are typically grown on bulk Cd1–x
Zn
x
Te substrates. Alternatively, epitaxial CdTe grown on Si or Ge has been used as a buffer layer for high-quality epitaxial
HgCdTe growth. In this paper, x-ray topographs and rocking-curve full-width at half-maximum (FWHM) data will be presented
for recent high-quality bulk CdZnTe grown by the vertical gradient freeze (VGF) method, previous bulk CdZnTe grown by the
vertical Bridgman technique, epitaxial CdTe buffer layers on Si and Ge, and a HgCdTe layer epitaxially grown on bulk VGF CdZnTe.
KeywordsCdZnTe-HgCdTe-CdTe-x-ray topography-x-ray diffraction-infrared
Journal of Electronic Materials 04/2012; 39(6):738-742. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: HgCdTe heteroepitaxy on low-cost, large-lattice-mismatched substrates such as Si continue to be plagued by large threading
dislocation densities that ultimately reduce the operability of the thermal imaging detector array. Molecular-beam epitaxy
(MBE) of 10 μm- to 15 μm-thick CdTe buffer layers has played a crucial role in reducing dislocation densities to current state-of-the-art levels.
Herein, we examine the possibility that growth on locally back-thinned substrates could prove advantageous in further reducing
dislocation densities in the CdTe/Si heteroepitaxial system. Using defect decoration techniques, a decrease in dislocation
(etch-pit) density of up to ~42% has been measured in CdTe regions where the underlying Si substrate was chemically back-thinned
to ~20μm. A theoretical understanding is proposed, where a substrate-thickness-dependent dislocation image force is a likely cause
for the experimentally observed reduction in threading dislocation density. These observations raise the prospect of combining
localized substrate thinning with other techniques to further reduce dislocation densities to levels sought for HgCdTe/CdTe/Si
and other large-lattice-mismatched systems.
KeywordsWafer thinning-threading dislocation density-mismatched heteroepitaxy-silicon-HgCdTe-CdTe-image force
Journal of Electronic Materials 04/2012; 39(7):1036-1042. · 1.47 Impact Factor
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J. D. Benson,
L. O. Bubulac,
P. J. Smith,
R. N. Jacobs, J. K. Markunas,
M. Jaime-Vasquez,
L. A. Almeida,
A. J. Stoltz,
P. S. Wijewarnasuriya,
G. Brill,
Y. Chen,
U. Lee,
M. F. Vilela,
J. Peterson,
S. M. Johnson,
D. D. Lofgreen,
D. Rhiger,
E. A. Patten,
P. M. Goetz
[show abstract]
[hide abstract]
ABSTRACT: The electrical performance of HgCdTe/Si photodiodes is shown not to have a direct relationship with the dislocation density
as revealed by defect etching. This has led to an equivalent circuit model to explain the relationship of the dislocation
density and the electrical test data. A new (112)B HgCdTe/CdTe/Si and CdTe/Si etch pit density (EPD) etch has been demonstrated.
The new etch has been used to look for distinctive features which may be responsible for the poor electrical performance of
individual diode pixels. The new etch chemistry also reduces the surface roughness of the etched epilayer and makes EPD determination
less problematic. The new (to HgCdTe) technique of electrostatic force microscopy has also been used to analyze the electrical
properties of dislocations.
KeywordsHgCdTe/CdTe/Si-molecular beam epitaxy-atomic force microscopy-electrostatic force microscopy-etch pit density
Journal of Electronic Materials 04/2012; 39(7):1080-1086. · 1.47 Impact Factor
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J. D. Benson,
P. J. Smith,
R. N. Jacobs, J. K. Markunas,
M. Jaime-Vasquez,
L. A. Almeida,
A. Stoltz,
L. O. Bubulac,
M. Groenert,
P. S. Wijewarnasuriya,
G. Brill,
Y. Chen,
U. Lee
[show abstract]
[hide abstract]
ABSTRACT: Scanning electron microscopy (SEM), atomic force microscopy (AFM), and x-ray diffraction (XRD) measurements all indicate an
approximate factor of ten increase in the Everson etch pit density (EPD) over standard Nomarski microscopy Everson EPD determination.
A new (112)B CdTe/Si EPD etch has also been demonstrated which reduces the surface roughness of the etched epilayer and makes
etch pit density determination less problematic.
Journal of Electronic Materials 04/2012; 38(8):1771-1775. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: X-ray diffraction full-width at half-maximum (XRD FWHM), reflection high-energy electron diffraction (RHEED), and atomic force
microscopy (AFM) indicate a mosaic structure for molecular-beam epitaxy (MBE) (211)B CdTe/Si. AFM measurements indicate long,
thin, small-angle-disoriented grains for CdTe/Si epilayers. These disoriented grains are ~1μm in the [[`1] 11 \overline{1} 11 ] direction and are ~40nm in the [01[`1] 01\overline{1} ] direction. The RHEED pattern in the [[`1] 11 \overline{1} 11 ] direction depicts nearly ideal single-crystal periodicity. The RHEED pattern in the [01[`1] 01\overline{1} ] direction is indicative of small-angle-disoriented crystalline grains. Scanning electron microscopy (SEM), AFM, and XRD
measurements all indicate an approximate factor of 10 increase in the Everson etch pit density (EPD) over standard Nomarski
microscopy Everson EPD determination.
Journal of Electronic Materials 08/2008; 37(9):1231-1236. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: Brief low-energy helium plasma exposure of mercury cadmium telluride and indium antimonide results in oxide- and elemental-component-free,
nearly stoichiometric surfaces. In these initial experiments, the only remaining residue is a topmost trace layer of carbon
similar to that present on wet etched and reduced surfaces. The nature of these surfaces was determined by in situ Auger electron spectroscopy, monochromatic X-ray photoelectron, and ion scattering spectroscopy, and compared with established
wet chemical and hydrogen argon plasma preparations.
Journal of Electronic Materials 01/2008; 37(2):152-156. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: Plasma etching of (112)B InSb to prepare this semiconductor for the heteroepitaxy deposition of CdTe and initial studies of
CdTe epilayers grown by molecular beam epitaxy (MBE) on InSb (112)B substrates cleaned with various plasma treatments are
presented. X-ray diffraction rocking curve maps of the MBE CdTe epilayers on 3-inch InSb (112)B substrates have full-width
at half-maxima (FWHM) values in the range of 20 arcsec to 30 arcsec. An etch pit density analysis of the 3-inch CdTe epilayers
reveals a defect density of 1.0×107 cm−2 and 7.7×105 cm−2 at the center and edge of the wafer, respectively. Evaluation of a standard HgCdTe annealing process suggests that the removal
of the InSb substrate is likely to be needed prior to any postgrowth annealing in Hg overpressure. Finally, we present a low-energy
helium plasma exposure of wet-etched InSb (112)B substrates that provides a uniform epi-ready surface that is nearly stoichiometric,
and free of oxide and residual contaminants.
Journal of Electronic Materials 01/2008; 37(9):1247-1254. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: The as-grown molecular beam epitaxy (MBE) (211)B HgCdTe surface has variable surface topography, which is primarily dependent
on substrate temperature and substrate/epilayer mismatch. Nano-ripple formation and cross-hatch patterning are the predominant
structural features observed. Nano-ripples preferentially form parallel to the [[`1]11] [\bar {1}11] and are from 0 Å to 100 Å in height with a wavelength between 0.1μm and 0.8μm. Cross-hatch patterns result from slip dislocations in the three {111} planes intersecting the (211) growth surface. The
cross-hatch step height is 4±1Å (limited data set). This indicates that only a bi-layer slip (Hg/Cd+Te) in the {111}
slip plane occurs. For the deposition of MBE (211)B HgCdTe/CdTe/Si, the reorientation of multiple nano-ripples coalesced into
“packets” forms cross-hatch patterns. The as-grown MBE (211)B CdTe/Si surface is highly variable but displays nano-ripples
and no cross-hatch pattern. Three types of defects were observed by atomic force microscopy (AFM): needle, void/hillock, and
voids.
Journal of Electronic Materials 01/2007; 36(8):949-957. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: The surface of (111)A HgCdTe has been studied by reflection high-energy electron diffraction and atomic force microscopy (AFM).
The as-grown liquid-phase epitaxy (LPE) surface has bilayer (3.7 ± 0.2 Å) step/terrace structures, macro-steps, and cross-hatch
patterns. Macro-steps occur about the
[11[`2]][11\bar 2]
and are from 10–40 Å in height. AFM and x-ray measurements indicate the as-grown epilayer is ≈0.2° off-cut (random polar
angle) from the (111). 〈110〉 cross-hatch lines consistent with bilayer (step height=3.9 ± 0.2 Å) {111} slip dislocation are
observed. The native oxide/carbon layer for the as-grown LPE (111)A HgCdTe is ≈8 Å. The experimental results suggest that
the as-grown LPE surface approximates an equilibrium vicinal crystal structure. The 0.1% Br:ethylene glycol wet chemically
etched surfaces retained the macro-step structure, but numerous small protrusions (10–100 Å height, ≈300 Å diameter) developed.
The plasma-etched (111)A HgCdTe surface is crystalline, but exhibits surface disorder and is roughened.
Journal of Electronic Materials 05/2006; 35(6):1434-1442. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: To investigate the potential benefits of compositional grading for dislocation control in CdTe/Si growth, Cd1−xZnxTe buffer layers with x graded smoothly from 1 to 0 have been deposited on Si (211) surfaces. Growth has been characterized
using reflection high-energy electron diffraction (RHEED), x-ray diffraction (XRD), and etch pit density measurements. XRD
showed an increase in rocking curve full-width at half-maximum (FWHM) and global lattice tilt with decreasing x values. Tilt
was also observed to increase as buffer growth temperature was increased. Final surface dislocation densities did not decrease
below 7×106 cm−2. EPD surface dislocation measurements showed reduced dislocation densities and dislocation clustering along the
[1[`1]0][1\bar 10]
and
[[`1]10][\bar 110]
lines for CdTe cap layers grown on partially graded Cd1−xZnxTe buffer layers with slow compositional grading rates. Samples grown with faster grading rates showed higher final EPD values,
with dislocations clustering along the
[31[`2]][31\bar 2]
and
[[`1][`3]2][\bar 1\bar 32]
lines.
Journal of Electronic Materials 01/2006; 35(6):1287-1292. · 1.47 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: (211) oriented silicon substrates were patterned and etched to give mesas of various sizes and shapes. Cadmium telluride epitaxial
layers were deposited on the patterned substrates by molecular beam epitaxy (MBE). Dislocation termini in the epilayer were
found to be concentrated in the trenches that formed the mesa boundaries. Mesa sizes up to 17 µm were found to be nearly free
of threading dislocation termini. Threading dislocation termini are observed to congregate in lines parallel to the 〈321〉
crystallographic directions. Evidence of subsurface, horizontal dislocations running through the mesa is given.
Journal of Electronic Materials 08/2005; 34(9):1242-1248. · 1.47 Impact Factor
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J. D. Benson,
A. J. Stoltz,
J. B. Varesi,
L. A. Almeida,
E. P. G. Smith,
S. M. Johnson,
M. Martinka,
A. W. Kaleczyc, J. K. Markunas,
P. R. Boyd,
J. H. Dinan
[show abstract]
[hide abstract]
ABSTRACT: The surface of (211)B HgCdTe has been studied by reflection high-energy electron diffraction (RHEED) and atomic force microscopy
(AFM). RHEED analysis of the as-grown Hg-rich molecular beam epitaxy (MBE) (211)B HgCdTe suggests the surface reconstructs
by additional Hg incorporation. The plasma-etched (211)B HgCdTe surface is crystalline but stepped and facetted. RHEED analysis
indicates asymmetric pyramids (base dimensions ≈0.5×1.1 nm) are formed to minimize surface Hg concentration. The AFM examination
of plasma-etched (211)B HgCdTe reveals oriented mesoscopic features.
Journal of Electronic Materials 05/2005; 34(6):726-732. · 1.47 Impact Factor
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M. Carmody,
J. G. Pasko,
D. Edwall,
M. Daraselia,
L. A. Almeida,
J. Molstad,
J. H. Dinan, J. K. Markunas,
Y. Chen,
G. Brill,
N. K. Dhar
[show abstract]
[hide abstract]
ABSTRACT: In the past several years, we have made significant progress in the growth of CdTe buffer layers on Si wafers using molecular
beam epitaxy (MBE) as well as the growth of HgCdTe onto this substrate as an alternative to the growth of HgCdTe on bulk CdZnTe
wafers. These developments have focused primarily on mid-wavelength infrared (MWIR) HgCdTe and have led to successful demonstrations
of high-performance 1024×1024 focal plane arrays (FPAs) using Rockwell Scientific’s double-layer planar heterostructure (DLPH)
architecture. We are currently attempting to extend the HgCdTe-on-Si technology to the long wavelength infrared (LWIR) and
very long wavelength infrared (VLWIR) regimes. This is made difficult because the large lattice-parameter mismatch between
Si and CdTe/HgCdTe results in a high density of threading dislocations (typically, >5E6 cm−2), and these dislocations act as conductive pathways for tunneling currents that reduce the RoA and increase the dark current of the diodes. To assess the current state of the LWIR art, we fabricated a set of test diodes
from LWIR HgCdTe grown on Si. Silicon wafers with either CdTe or CdSeTe buffer layers were used. Test results at both 78 K
and 40 K are presented and discussed in terms of threading dislocation density. Diode characteristics are compared with LWIR
HgCdTe grown on bulk CdZnTe.
Journal of Electronic Materials 05/2004; 33(6):531-537. · 1.47 Impact Factor
