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ABSTRACT: We present a pattern recognition methodology based on stochastic logic. The technique implements a parallel comparison of input data from a set of sensors to various pre-stored categories. Smart pulse-based stochastic-logic blocks are constructed to provide an efficient architecture that is able to implement Bayesian techniques, thus providing a low-cost solution in terms of gate count and power dissipation. The proposed architecture is applied to a specific navigation problem demonstrating that the system provides an almost optimal solution.
Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on; 07/2008
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ABSTRACT: A BIST architecture is presented to perform charge-based testing (BIST-CBT) on embedded memories where direct access to I/Os is limited. The proposed architecture includes a charge monitor, a functional test algorithm generator (that applies a standard March B algorithm) and output processing circuitry. The method is based on a charge correlation technique validated experimentally on previous works for submicron SRAMs. The testing methodology implementation has two phases: a short pre-characterisation phase performed during manufacturing test to ensure process-variation immunity, and the actual BIST-CBT. Data from the first phase are processed and loaded in the BIST circuitry registers. The proposed embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the functional and BIST charge analysis (both based on the same March algorithms). To demonstrate the viability of the proposed architecture, a prototype is designed that has been implemented in two parts: the charge monitor is the core of the BIST circuitry, and has been developed in 120 nm CMOS technology, whereas the digital processing circuitry has been implemented on a FPGA device.
IET Computers & Digital Techniques 10/2007; · 0.45 Impact Factor
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ABSTRACT: A chaotic IC is proposed and fabricated using a 0.35 mum CMOS technology. The circuit iterates an N-shaped transfer function that can be modified using two external voltages, and is implemented using a three neurons network. The main advantages of the proposed circuit are based on its simplicity, small area (47 times 57 mum<sup>2</sup>), and its MOS-only implementation requiring no more than 15 MOS transistors. Measurements show the suitability of the proposed system to reproduce a chaotic signal and to be used as a random number generator.
Neural Networks, 2006. IJCNN '06. International Joint Conference on; 01/2006
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ABSTRACT: We present a BIST architecture to perform charge based analysis on embedded memories. The architecture includes a charge monitor as well as the input generation and output processing circuitry. The method applies a charge correlation technique, validated experimentally on previous works for submicron SRAMs. The technique requires a short pre-characterization phase during manufacturing testing that guarantees process-variation immunity. The embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the BIST-charge analysis.
On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International; 08/2004
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ABSTRACT: We evaluated a diagnostic technique based on the charge delivered to the IC during a transition. Charge computed from the transient supply current is related to the circuit internal activity. A specific activity can be forced into the circuit using appropriate test vectors to highlight possible defect locations. Experimental results from a small test circuit and a 256 K SRAM demonstrate the experimental viability of the technique. The theoretical foundation is also discussed
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001; 02/2001
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ABSTRACT: A transient current testing technique that computes the charge
delivered to the circuit during the transient circuit operation is
analyzed. The method is applied to 0.5 μm CMOS SRAMs with 1.5 million
transistors that passed various logic tests. Results show that Charge
Based Testing (CBT) can be used to test submicron ICs and can be applied
to non fully static parts
Defect Based Testing, 2000. Proceedings. 2000 IEEE International Workshop on; 02/2000
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ABSTRACT: This work presents a prototype architecture that provides on-line
IDDQ measurement for a microprocessor-based system. It has been
implemented using an IDDQ testable microprocessor (the Intel 386<sup>TM
</sup> EX embedded microprocessor) and an off-chip current sensor. Three
current test activation modes are supported. A direct test mode through
a sensor dedicated pin, a test mode where the microprocessor controls
the off-chip sensor, and a P1149.1 driven test. Measurements and
architecture operation are detailed
On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International; 02/2000
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ABSTRACT: A test technique that uses the charge driven into the circuit
computed from the transient power supply current is analysed.
Experimental data are provided concerning the merits of this technique
and its effectiveness at detecting open defects that do not increase the
power consumption (those that cannot be detected with I<sub>DDQ</sub>)
Electronics Letters 04/1999; · 0.96 Impact Factor
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ABSTRACT: We evaluated a technique that uses power supply charge as the test
observable. Charge was computed from the measured supply transient
current waveform. Data show that this method is efficient to detect
those defects that prevent current elevation (mainly “hard”
opens) and therefore represents a valid extension of I<sub>DDQ</sub>
IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on; 12/1998
