I. de Paul

University of the Balearic Islands, Palma, Balearic Islands, Spain

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Publications (16)5.8 Total impact

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    ABSTRACT: Background: The electronic nose (e-nose) detects volatile organic compounds (VOCs) in exhaled air. We hypothesized that the exhaled VOCs print is different in stable vs. exacerbated patients with chronic obstructive pulmonary disease (COPD), particularly if the latter is associated with airway bacterial infection, and that the e-nose can distinguish them. Methods: Smell-prints of the bacteria most commonly involved in exacerbations of COPD (ECOPD) were identified in vitro. Subsequently, we tested our hypothesis in 93 patients with ECOPD, 19 of them with pneumonia, 50 with stable COPD and 30 healthy controls in a cross-sectional case-controlled study. Secondly, ECOPD patients were re-studied after 2 months if clinically stable. Exhaled air was collected within a Tedlar bag and processed by a Cynarose 320 e-nose. Breath-prints were analyzed by Linear Discriminant Analysis (LDA) with "One Out" technique and Sensor logic Relations (SLR). Sputum samples were collected for culture. Results: ECOPD with evidence of infection were significantly distinguishable from non-infected ECOPD (p = 0.018), with better accuracy when ECOPD was associated to pneumonia. The same patients with ECOPD were significantly distinguishable from stable COPD during follow-up (p = 0.018), unless the patient was colonized. Additionally, breath-prints from COPD patients were significantly distinguished from healthy controls. Various bacteria species were identified in culture but the e-nose was unable to identify accurately the bacteria smell-print in infected patients. Conclusion: E-nose can identify ECOPD, especially if associated with airway bacterial infection or pneumonia.
    PLoS ONE 09/2015; 10(9):e0135199. DOI:10.1371/journal.pone.0135199 · 3.23 Impact Factor
  • I. De Paul · F.N. Bandi · J. Segura · S.A. Bota ·
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    ABSTRACT: We perform a comparative study of the characteristics and capabilities of a pulsed laser system that emulates single event injection available at the UIB with respect to similar pulsed laser test facilities in Europe (EADS, IMS) and the United States (JPL, NRL). A series of experimental measurements were taken on a silicon photodiode (Centronic OSD15-5T) used in a previous comparative study conducted by the mentioned centers.
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    ABSTRACT: Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter -the word-line voltage margin (V-WLVM)- and the measured circuit alpha-SER. Additional experiments show that no other memory cell electrical robustness-related parameters exhibit such correlation. The technique proposed is based on correlating the V-WLVM to the SER measured on a small number of circuit samples to determine the correlation parameters. Then, the remaining non-irradiated circuits SER is determined from electrical measurements (V-WLVM) without the need of additional radiation experiments. This method represents a significant improvement in time and cost, while simplifying the SER-determination methods since most of the circuits do not require irradiation. The technique involves a minor memory design modification that does not degrade circuit performance, while circuit area increase is negligible.
    IEEE Transactions on Nuclear Science 08/2014; 61(4):1849-1855. DOI:10.1109/TNS.2014.2311697 · 1.28 Impact Factor
  • S.A. Bota · G. Torrens · I. de Paul · B. Alorda · L.A. Segura ·
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    ABSTRACT: Radiation sensitivity of SRAM memories is of vital importance in applications demanding high reliability levels. Soft error rates (SER) are usually determined through accelerated tests where target devices are subjected to very high levels of radiation, in order to increase the number of induced events. Two main factors determine the accuracy of this technique, on one hand, when the number of induced events is low the result is subjected to statistical errors, on the other hand, if the number of induced events is high, the probability that each cell experiences more than one event is increased, as a result there is the risk that a fraction of the events will not be counted. In this paper we propose an accelerated test method to determine the soft error rate in SRAM memories from a model based on the evolution of the cell population being at logic zero (or logic one) during the irradiation experiment. This model has been contrasted with experimental results obtaining a very good correlation.
    On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International; 01/2013
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    ABSTRACT: In this work we provide design guidelines for the hardware implementation of Spiking Neural Networks. The proposed methodology is applied to temporal pattern recognition analysis. For this purpose the networks are trained using a simplified Genetic Algorithm. The proposed solution is applied to estimate the processing efficiency of Spiking Neural Networks.
    Artificial Neural Networks - ICANN 2009, 19th International Conference, Limassol, Cyprus, September 14-17, 2009, Proceedings, Part I; 01/2009
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    ABSTRACT: This work provides practical guidelines for an efficient hardware implementation of Neural Networks. Networks are configured using a practical self-learning architecture that iterates a basic Genetic Algorithm. The learning methodology is based on the generation of random vectors that can be extracted from chaotic signals. The proposed solution is applied to estimate the processing efficiency of Spiking Neural Networks.
    Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part III; 01/2009
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    J.L. Rossello · Vincent Canals · Ivan de Paul · Jaume Segura ·
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    ABSTRACT: We present a pattern recognition methodology based on stochastic logic. The technique implements a parallel comparison of input data from a set of sensors to various pre-stored categories. Smart pulse-based stochastic-logic blocks are constructed to provide an efficient architecture that is able to implement Bayesian techniques, thus providing a low-cost solution in terms of gate count and power dissipation. The proposed architecture is applied to a specific navigation problem demonstrating that the system provides an almost optimal solution.
    Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on; 07/2008
  • B. Alorda · I. de Paul · J. Segura ·
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    ABSTRACT: A BIST architecture is presented to perform charge-based testing (BIST-CBT) on embedded memories where direct access to I/Os is limited. The proposed architecture includes a charge monitor, a functional test algorithm generator (that applies a standard March B algorithm) and output processing circuitry. The method is based on a charge correlation technique validated experimentally on previous works for submicron SRAMs. The testing methodology implementation has two phases: a short pre-characterisation phase performed during manufacturing test to ensure process-variation immunity, and the actual BIST-CBT. Data from the first phase are processed and loaded in the BIST circuitry registers. The proposed embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the functional and BIST charge analysis (both based on the same March algorithms). To demonstrate the viability of the proposed architecture, a prototype is designed that has been implemented in two parts: the charge monitor is the core of the BIST circuitry, and has been developed in 120 nm CMOS technology, whereas the digital processing circuitry has been implemented on a FPGA device.
    IET Computers & Digital Techniques 10/2007; 1(5-1):481 - 490. DOI:10.1049/iet-cdt:20060058 · 0.36 Impact Factor
  • Bartomeu Alorda · Ivan de Paúl · Jaume Segura ·

  • J.L. Rossello · S. Bota · V. Canals · I. de Paul · J. Segura ·
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    ABSTRACT: A chaotic IC is proposed and fabricated using a 0.35 mum CMOS technology. The circuit iterates an N-shaped transfer function that can be modified using two external voltages, and is implemented using a three neurons network. The main advantages of the proposed circuit are based on its simplicity, small area (47 times 57 mum<sup>2</sup>), and its MOS-only implementation requiring no more than 15 MOS transistors. Measurements show the suitability of the proposed system to reproduce a chaotic signal and to be used as a random number generator.
    Neural Networks, 2006. IJCNN '06. International Joint Conference on; 01/2006
  • B. Alorda · V. Canals · I. de Paul · J. Segura ·
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    ABSTRACT: We present a BIST architecture to perform charge based analysis on embedded memories. The architecture includes a charge monitor as well as the input generation and output processing circuitry. The method applies a charge correlation technique, validated experimentally on previous works for submicron SRAMs. The technique requires a short pre-characterization phase during manufacturing testing that guarantees process-variation immunity. The embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the BIST-charge analysis.
    On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International; 08/2004
  • I. de Paúl · M. Rosales · B. Alorda · J. Segura · C. Hawkins · J. Soden ·
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    ABSTRACT: We evaluated a diagnostic technique based on the charge delivered to the IC during a transition. Charge computed from the transient supply current is related to the circuit internal activity. A specific activity can be forced into the circuit using appropriate test vectors to highlight possible defect locations. Experimental results from a small test circuit and a 256K SRAM demonstrate the experimental viability of the technique. The theoretical foundation is also discussed.
  • B. Alorda · I. de Paul · J. Segura · T. Miller ·
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    ABSTRACT: This work presents a prototype architecture that provides on-line IDDQ measurement for a microprocessor-based system. It has been implemented using an IDDQ testable microprocessor (the Intel 386<sup>TM </sup> EX embedded microprocessor) and an off-chip current sensor. Three current test activation modes are supported. A direct test mode through a sensor dedicated pin, a test mode where the microprocessor controls the off-chip sensor, and a P1149.1 driven test. Measurements and architecture operation are detailed
    On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International; 02/2000
  • M. Rosales · I. de Paul · J. Segura · C.F. Hawkins · J. Soden ·
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    ABSTRACT: A transient current testing technique that computes the charge delivered to the circuit during the transient circuit operation is analyzed. The method is applied to 0.5 μm CMOS SRAMs with 1.5 million transistors that passed various logic tests. Results show that Charge Based Testing (CBT) can be used to test submicron ICs and can be applied to non fully static parts
    Defect Based Testing, 2000. Proceedings. 2000 IEEE International Workshop on; 02/2000
  • J. Segura · I. De Paul · M. Roca · E. Isern · C.F. Hawkins ·
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    ABSTRACT: A test technique that uses the charge driven into the circuit computed from the transient power supply current is analysed. Experimental data are provided concerning the merits of this technique and its effectiveness at detecting open defects that do not increase the power consumption (those that cannot be detected with I<sub>DDQ</sub>)
    Electronics Letters 04/1999; 35(6-35):441 - 443. DOI:10.1049/el:19990359 · 0.93 Impact Factor
  • I. de Paul · R. Picos · J.L. Rossello · M. Roca · E. Isern · J. Segura · C.F. Hawkins ·
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    ABSTRACT: We evaluated a technique that uses power supply charge as the test observable. Charge was computed from the measured supply transient current waveform. Data show that this method is efficient to detect those defects that prevent current elevation (mainly “hard” opens) and therefore represents a valid extension of I<sub>DDQ</sub>
    IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on; 12/1998