[show abstract][hide abstract] ABSTRACT: Dual-material gate MOSFET with dielectric pockets (DMGDP MOSFET) is proposed to eliminate the potential weakness of the DP
MOSFET for CMOS scaling toward the 32 nm gate length and beyond. The short-channel effects (SCE) can be effectively suppressed
by the insulator near the source/drain regions. And the suppression capability can be even better than the DP MOSFET due to
the drain bias absorbed by the screen gate. The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively
studied. Compared to the experimental data from Jurczak et al., the DMGDP PMOSFET exhibits good subthreshold characteristics
and the on-state current is almost the twice that of the DP PMOSFET. The intrinsic delay of the NMOS reaches 21% greater than
the DP MOSFET for 32 nm node. The higher f
T of 390 GHz is achieved, which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm. Finally,
the design guideline and the optimal regions of the DMGDP MOSFET are discussed.
Science in China Series E Technological Sciences 04/2012; 52(8):2400-2405. · 1.02 Impact Factor
[show abstract][hide abstract] ABSTRACT: A two-dimensional (2D) model for the subthreshold current in the dual-material gate (DMG) silicon-on- insulator (SOI) MOSFET
with a single halo is presented. The model considers single halo doping in the channel near the source and a dual-material
gate to derive the channel potential using the explicit solution of the 2D Poisson’s equation. Together with the conventional
drift-diffusion theory, this results in the development of a subthreshold current model for the novel structure. Model verification
is carried out using the 2D device simulator ISE. Excellent agreement is obtained between the calculations and the simulated
results of the model.
Frontiers of Electrical and Electronic Engineering in China 02/2009; 4(1):98-103.