Publications (3)4.19 Total impact
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Article: A 1.8~3.2-GHz fully differential GaAs MESFET PLL
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ABSTRACT: A 1.8~3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74~3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8~3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHzIEEE Journal of Solid-State Circuits 05/2001; · 3.23 Impact Factor -
Conference Proceeding: A novel charge pump PLL with reduced jitter characteristics
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ABSTRACT: A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 μm CMOS process technology and evaluated by post-layout simulationVLSI and CAD, 1999. ICVC '99. 6th International Conference on; 02/1999 -
Article: Phase/frequency detectors for high-speed PLL applications
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ABSTRACT: Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32 ns and the other a reset time of 0.03 ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8 μm CMOS process parametersElectronics Letters 11/1998; · 0.96 Impact Factor
Top co-authors
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Institutions
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1998–2001
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Yonsei University
- Department of Electrical and Electronic Engineering
Seoul, Seoul, South Korea
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