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ABSTRACT: The performance of a system depends heavily on the communication speed between integrated circuits. One of the most important bottlenecks that limit the communication speed is simultaneous switching noise (SSN). A major contribution to SSN is return path discontinuities, which are caused by the change or disruption in return currents due to via transitions, aperture effects, etc. In this paper, a new concept based on power transmission line (PTL) is proposed to supply power, improve signal and power integrity, and enhance chip-to-chip communication speed. The first demonstration of constant current PTL (CCPTL)-based single-ended signaling scheme is implemented and measured. The results show that the CCPTL scheme improves the quality of the received signal in terms of voltage and timing margin.
IEEE Transactions on Electromagnetic Compatibility 12/2011; · 1.18 Impact Factor
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ABSTRACT: Due to the increasing operating frequency and power density, more current is being drawn from the power delivery network (PDN). For off-chip signaling, the drawn current flows through the signal transmission line outside the chip, and induces a return current on the reference plane. The power planes cause return path discontinuity (RPD), which induces power noise and coupling between the signal distribution network and the PDN. In this paper, a transmission line structure is proposed to replace the power plane and convey power supply from the voltage source to each integrated circuit (IC), which is called as Power Transmission Line (PTL). In this paper, proof of concept for the Constant Current Power Transmission Line (CCPTL) based single-ended signaling scheme is presented. The efficacy of using PTL is verified by measurement results.
Signal Propagation on Interconnects (SPI), 2011 15th IEEE Workshop on; 06/2011
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ABSTRACT: Two research projects are described that develop low-cost techniques for testing multi-gigahertz devices. Each project uses commercially available components to keep costs low, and achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. An FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized emitter-coupled logic achieves multi-gigahertz data rates with about ±25ps timing accuracy. This paper has been adapted from (Keezer, 2005).
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European; 10/2005
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ABSTRACT: Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages (SOPs) very difficult. Testing packages with multigigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an "intelligent" manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented.
IEEE Transactions on Advanced Packaging 06/2004; · 1.12 Impact Factor
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R.R. Tummala,
M. Swaminathan,
M.M. Tentzeris,
J. Laskar,
Gee-Kung Chang,
S. Sitaraman, D. Keezer,
D. Guidotti,
Zhaoran Huang,
Kyutae Lim,
Lixi Wan,
S.K. Bhattacharya,
V. Sundaram,
Fuhan Liu,
P.M. Raj
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ABSTRACT: From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical-
test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.
IEEE Transactions on Advanced Packaging 06/2004; · 1.12 Impact Factor
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ABSTRACT: This paper describes a new high throughput test methodology for a new multi-chip module (MCM) substrate. This is based on a new MCM substrate technology which contains interconnects, embedded passive devices, and mixed-signal circuits, currently being developed by the Packaging Research Center at Georgia Tech. The resulting MCM modules are called SLIM (single layer integrated module). In this paper a best methodology for SLIM modules is discussed
Test Conference, 1998. Proceedings., International; 11/1998
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ABSTRACT: Scene matching is the problem of matching regions of two images of
the same scene taken by different sensors at different times or under
different viewing conditions. Hierarchical scene matching is a technique
for reducing the amount of computation involved in scene matching
applications. Most of the past research on this problem has concentrated
on efficient software algorithms, and very little effort has been
expended on custom hardware solutions. We describe the design of SMAC, a
new VLSI architecture for Hierarchical Scene Matching. This architecture
achieves a significant amount of speedup by utilizing a large amount of
parallelism and pipelining. The paper also describes the design and
implementation of a prototype CMOS VLSI chip that implements the
exhaustive search task of the scene matching algorithm
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on; 11/1993
