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ABSTRACT: In this article, the electrical properties of 3C-SiC are described and its potential for metal-oxide semiconductor field-effect transistors (MOSFETs) is demonstrated. The density of traps, DIT, at the interface of 3C-SiC/SiO2 capacitors is determined by the conductance method subsequent to various processing steps; the origin of the interface traps is discussed. Lateral and vertical 3C-SiC MOSFET devices of varying cell and device size are designed with hexagonal and squared cell geometry, and are fabricated side by side with MOS Hall bar structures. The electrical parameters of the MOSFETs are determined, and the free electron areal density and Hall mobility are measured in the channel of the MOS Hall bar structures. Based on the charge-sheet model, DIT is also obtained from the Hall investigations.
Chemical Vapor Deposition 08/2006; 12(8‐9):523 - 530. · 1.80 Impact Factor
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ABSTRACT: The planar defects that occur at the 3C–SiC/Si(001) interface can be classified as anti-phase boundary (APB) and stacking-fault (SF). In order to reduce SFs and APBs simultaneously, 3C–SiC is grown on undulant-Si in which the surface is covered with continuous slopes oriented in the [110] and [0] directions. This eliminates APBs at each slope of an undulation via step-flow epitaxy. In addition, SFs with an exposed C-face on the (001) surface (SFC) are eliminated via self-vanishing, while those with an exposed Si-face on the (001) surface (SFSi) form triangular shapes that expand with increasing 3C–SiC thickness. To remove any SFSi that cannot be eliminated on the undulant Si, an advanced SF reduction method involving homoepitaxial growth, called switch-back epitaxy (SBE), is investigated.
Chemical Vapor Deposition 08/2006; 12(8‐9):502 - 508. · 1.80 Impact Factor
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ABSTRACT: Attempts to grow mono-crystalline cubic silicon carbide (3C-SiC) have been made using vapor phase hetero-epitaxial growth with Si [1], TiC [2], and sapphire [3] as substrates, and with bulk growth using the sublimation method. In 1983, Nishino et al. reported hetero-epitaxial growth
of 3C-SiC on a carbonized Si(001) surface [5]. Since then, 3C-SiC heteroepitaxy on Si substrate using the CVD or MBE methods has been studied intensively, because it has been proved that
using Si as a substrate facilitates the upsizing of SiC, while reducing manufacturing costs, and that carbonization of the
Si surface significantly improves the reproducibility of the 3C-SiC grown on it.
12/2003: pages 207-228;
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ABSTRACT: The heteroepitaxial growth of 3C-SiC on Si(001) substrates has been studied in a hot-wall-type low-pressure reactor. The Si substrates were carbonized by C2H2 prior to the SiC growth process to suppress the undesirable effects of lattice mismatching between Si and 3C-SiC. A single-crystal carbonized layer (3C-SiC) was obtained from 500 °C to higher than 1000 °C in an C2H2 environment. Following the carbonization process, SiH2Cl2 and C2H2 were alternately supplied into the reaction tube to grow an epitaxial 3C-SiC film. The growth rate of 3C-SiC depended on the amount of Si incorporated into the surface of the substrates by H2 reduction of SiCl2 as a Si precursor. The “H2 intermittent flow” method employed during the SiC growth process efficiently suppressed the reduction of SiCl2 and induced a constant growth rate of the SiC. The crystallinity of the grown 3C-SiC films on Si substrates was evaluated using transmission electron microscopy, selected-area electron diffraction, and X-ray diffraction methods. The grown 3C-SiC films included anti-phase boundaries and twins. The concentration of these plane defects decreased due to coalescence with each other during SiC growth and resulted in an improvement in crystallinity and electrical properties.
physica status solidi (b) 06/1997; 202(1):335 - 358. · 1.32 Impact Factor
