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ABSTRACT: A 3.3V, 0.8 mW programmable Numerical Controlled oscillator Oscillator (NCO) core is designed in 0.6 micron CMOS process and
its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers
that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the NCO is analyzed.
Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using
faster FPGA devices or by implementing it on an advanced deep-submicron process.
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings; 01/2003