E.M.C. Filho

Publications (7)0 Total impact

• Conference Proceeding: The dynamic trace memoization reuse technique

  A.T. da Costa, F.M.G. Franca, E.M.C. Filho
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  ABSTRACT: Dynamic Trace Memoization (DTM) is a reuse technique that employs memoization tables to skip the execution of sequences of redundant instructions. For the SPECInt95 benchmark programs, DTM delivers performance improvements from 5% to 21% with an average of 9.3%. Moreover, DTM attains twice the average speedup of two other previously proposed reuse mechanisms for a subset of the SPECInt95 benchmarks
  Parallel Architectures and Compilation Techniques, 2000. Proceedings. International Conference on; 02/2000
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  Available from: uci.edu

  Conference Proceeding: The MorphoSys dynamically reconfigurable system-on-chip

  Guangming Lu, H. Singh, Ming-Hau Lee, N. Bagherzadeh, F.J. Kurdahi, E.M.C. Filho, V. Castro-Alves
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  ABSTRACT: MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors. Meanwhile, MorphoSys can provide the potential hardware platforn for the evolvable hardware (EH) simulation with the help of the software
  Evolvable Hardware, 1999. Proceedings of the First NASA/DoD Workshop on; 02/1999
• Conference Proceeding: HiPCrypto: a high-performance VLSI cryptographic chip

  S.L.C. Salomao, V.C. Alves, E.M.C. Filho
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  ABSTRACT: Data security is an important issue in today's computer networks. This paper presents the HiPCrypto chip, which implements the IDEA cryptographic algorithm. HiPCrypto is oriented towards computer network applications demanding high throughput. Its architecture exploits both the spatial and the temporal parallelism available in the IDEA algorithm. When operating at a 53 MHz clock, HiPCrypto can encrypt/decrypt at data rates up to 3.4 Gbps
  ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International; 10/1998
• Conference Proceeding: Load balancing in superscalar architectures

  E.M.C. Filho, E.S.T. Fernandes, A. Wolfe
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  ABSTRACT: New techniques are increasing the degree of instruction-level parallelism exploited by processors. Recent superscalar implementations include multiple functional units, allowing the parallel execution of several instructions from the same application program. The trend towards an expansion of the number of hardware resources is likely to continue in future superscalar designs, and in order to maximize the processor throughput, the computational load must be balanced among these resources by the dynamic instruction-issuing algorithm. We investigate the effect on performance caused by the way instructions are distributed among the functional units of superscalar processors. Our results show that a performance gain of up to 38% can be obtained when the instructions are evenly distributed among the functional units
  EUROMICRO 96. 'Beyond 2000: Hardware and Software Design Strategies'., Proceedings of the 22nd EUROMICRO Conference; 10/1996
• Conference Proceeding: A two-level pipelined implementation of the IDEA cryptographic algorithm

  S.L.C. Salomao, V.C. Alves, E.M.C. Filho
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  ABSTRACT: Data security is an important issue in today's computer networks. This paper presents the HiPCrypto chip, which implements the IDEA cryptographic algorithm. HiPCrypto is oriented towards computer network applications demanding high throughput. Its architecture exploits both the spatial and the temporal parallelism available in the IDEA algorithm. When operating with a 53 MHz clock, HiPCrypto can encrypt/decrypt at data rates up to 3.4 Gbps
  Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on;
• Conference Proceeding: Designing the dispatch stage of a superscalar microprocessor

  J.M.S. Alcantara, V.C. Alves, E.M.C. Filho
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  ABSTRACT: The design of a superscalar microprocessor poses several challenging problems concerning both its architectural conception and VLSI implementation. This paper discusses the main aspects in the design of the dispatch stage of the Superflux superscalar processor. First, it presents a methodology directed to the cooperative development of a large VLSI project. Then, it shows how the methodology is applied to the design of Superflux's dispatch stage. The approach described can be immediately applied or easily adapted/extended to other large VLSI designs. Although superscalar processors are now present in systems from microcomputers to large multiprocessors, few papers have been published about the practical design of these devices. This paper contributes with an introductory view to this task
  Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on;
• Conference Proceeding: MorphoSys: a reconfigurable architecture for multimedia applications

  H. Singh, Ming-Hau Lee, Guangming Lu, F.J. Kurdahi, N. Bagherzadeh, E.M.C. Filho
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  ABSTRACT: We describe the MorphoSys reconfigurable system, which combines a reconfigurable array of processor cells with a RISC processor core and a high bandwidth memory interface unit. We introduce the array architecture, its configuration memory, inter-connection network, role of the control processor and related components. Architecture implementation is described in brief and the efficacy of MorphoSys is demonstrated through simulation of video compression (MPEG-2) and target-recognition applications. Comparison with other implementations illustrates that MorphoSys achieves higher performance by up to 10X
  Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on;