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ABSTRACT: Addressing applications such as high performance RF power amplifiers and DC/DC converters with high conversion efficiency we demonstrate a cost effective integration of a complementary medium voltage RF LDMOS module in a 0.25 μm base CMOS flow. The integration of the NLDMOS and PLDMOS transistors requires just three additional mask steps. The NLDMOS has an excellent large signal RF performance up to 6 GHz. Key RF performance figures at 1 dB gain compression are 20 dB gain, 35 % power added efficiency and 0.4 W/mm power density. First prototypes of fabricated 12 V DC/DC down converters and 6 GHz power amplifiers verify the excellent DC and RF performance of the devices.
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11th Topical Meeting on; 02/2011
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ABSTRACT: The analysis, design, and evaluation of medium-voltage laterally diffused metal oxide semiconductor (LDMOS) transistors for wireless applications up to 6 GHz is presented. Using an optimized N-LDMOS transistor, power devices of different transistor geometries were fabricated in a standard 0.25-μm bipolar complementary metal oxide semiconductor (BiCMOS) technology with and without on-chip stabilization networks. The influences of the finger geometry and the stabilization networks on the RF performance were studied based on small-signal and large-signal on-wafer measurements. It was analytically shown and experimentally verified that transistor geometries with reduced gate width per finger but higher number of fingers are advantageous regarding the maximum oscillation frequency. From the source/load-pull characterization of a 1.8-mm total gate-width device, state-of-the-art, large-signal performance with a maximum output power of 29.7 dBm and a peak drain efficiency of 44% were obtained at 5.8 GHz. Power evaluation of the LDMOS transistors was also carried out in designed hybrid power amplifier modules targeted for vehicular wireless LAN applications. In the 5.8-5.9 GHz band, an output power of 1 W at 1-dB power compression, an adjacent channel power ratio of -38 dBc and an error vector magnitude of 3% at 1 dB peak power compression are reported.
IEEE Transactions on Microwave Theory and Techniques 01/2011; · 1.85 Impact Factor
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ABSTRACT: We present radiation hardness studies performed on LDMOS devices included in a 0.25 μm SiGe BiCMOS technology from IHP Microelectronics. Results show degradation of devices performances only beyond 1 × 10<sup>15</sup> n<sub>eq</sub>/cm<sup>2</sup>.
IEEE Transactions on Nuclear Science 01/2011; · 1.45 Impact Factor
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ABSTRACT: The design and characterization of CMOS compatible medium voltage LDMOS transistors are presented. Devices of different sizes were fabricated in a 0.25 μm BiCMOS technology and were characterized in the most important wireless telecommunication bands up to 5.8 GHz using a load/source pull measurement setup. Alternative layouts with regards to device geometry and stabilizing networks were investigated. Some of the transistors were equipped with on-chip stability networks to guarantee safe operation over the whole frequency band. This is shown to be established without substantial performance degradation. The medium size 1.8 mm device shows state-of-the-art performance over bandwidth with peak drain efficiencies of 51%, 44% at 2.66 GHz, 5.8 GHz providing a saturated output power of 30.1 dBm, 29.7 dBm. The linearity performance at all bands was investigated by determining the adjacent channel power ratio for a WCDMA test signal. The excellent RF performance achieved is verified in a real design by means of a hybrid class-AB power amplifier operating at 5.8 GHz.
Microwave Integrated Circuits Conference (EuMIC), 2010 European; 10/2010
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ABSTRACT: TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radiation expected for an upgrade to the LHC experiments. TID induces threshold voltage shifts and, in n-channel transistors, source-drain leakage currents. Wide variability in the magnitude of these effects is observed. Displacement damage increases the on-resistance of both vertical and lateral high-voltage transistors. In the latter case, degradation at high particle fluence might lead to a distortion of the output characteristics curve. HBD techniques to limit or eliminate the radiation-induced leakage currents are successfully applied to these high-voltage transistors, but have to be used carefully to avoid consequences on the breakdown voltage.
IEEE Transactions on Nuclear Science 09/2010; · 1.45 Impact Factor
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ABSTRACT: The design and characterization of LDMOS power transistors and amplifiers developed for 6 GHz WLAN applications are presented. Transistors of different size were fabricated in a 0.25 μm SiGe:C BiCMOS technology and have been characterized using a load/source pull measurement system. Based on this characterization a 5.8-5.9 GHz power amplifier was designed, fabricated and tested. By using on-board Wilkinson combiner structures an output power of 1 W at 1 dB power compression was achieved. The measured maximum drain efficiency/PAE were 40/28 % with a small signal gain of 7.2 dB. From the modulated signal evaluation using a 802.11p test signal an ACPR of -38 dBc and an error vector magnitude of 3 % were determined at 1 dB peak power compression.
Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International; 06/2010
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ABSTRACT: This work presents the design and characterization of medium voltage LDMOS transistors developed for 5-6 GHz power amplifier applications. Power transistors of different size have been fabricated in a 0.25 μm BiCMOS technology of IHP microelectronics and were characterized using a load/source pull measurement system. The optimum load and source impedances obtained for a 1.1 mm device provide the basis for a 6 GHz power amplifier design with an output power of 27.8 dBm in saturation and 25.1 dBm at 1 dB power compression. The peak drain efficiency of this power amplifier is 25.5% with a small signal gain of 8.1 dB.
German Microwave Conference, 2010; 04/2010
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ABSTRACT: TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radiation expected for an upgrade to the LHC experiments. TID induces threshold voltage shifts and, in n-channel transistors, source-drain leakage currents. Wide variability in the magnitude of these effects is observed. Displacement damage increases the on-resistance of both vertical and lateral high-voltage transistors. In the latter case, degradation at high particle fluence might lead to a distortion of the output characteristics curve. HBD techniques to limit or eliminate the radiation-induced leakage currents are successfully applied to these high-voltage transistors, but have to be used carefully to avoid consequences on the breakdown voltage.
Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on; 10/2009
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ABSTRACT: In this paper, we study the influence of the doping profile in the drift region on performance and reliability of RF-NLDMOS transistors in a 0.13 mum SiGe-BiCMOS technology. Two different drift region designs were investigated by simulation and experiment. We show that the design with a shallow compensation implant delivers a significantly improved HCI robustness at a similar level of RF and DC performance. The presented modular integration concept offers NLDMOS devices with breakdown-voltages BV<sub>DSS</sub>=21 V and peak cut-off frequencies f<sub>T</sub>=23 GHz. The maximum operating voltage for less than 10% degradation of the on-resistance in ten years is 11 V.
Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
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ABSTRACT: Abstract - A new cost-effective concept for RF-LDMOS transistors in a standard 0.13 mum CMOS technology without process modifications is demonstrated. For the integration of the devices only standard implants of the RF-CMOS process are used. The devices have gate length of 0.35 mum and share the 7 nm gate oxide of the 3.3 V CMOS I/O devices. A breakdown voltage of 19 V and f<sub>T</sub>/f<sub>MAX</sub> values of 25 GHz/55 GHz, respectively are obtained.
Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on; 02/2009
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ABSTRACT: Sr-Ta-O thin films were deposited as high-k dielectrics for metal-insulator-metal applications on 200-mm TiN/Si(100) substrates from a single-source Sr[Ta(OEt)<sub>5</sub>(methoxyethoxide)]<sub>2</sub> precursor using atomic vapor deposition technique. The variation of process pressure affects the Sr/Ta ratio in the films. Dielectric layers with optimized composition of Sr<sub>2</sub>Ta<sub>2</sub>O<sub>7-delta</sub> possess a capacitance density of 5.5 fF/mum<sup>2</sup> in combination with a voltage linearity coefficient of 80 ppm/V<sup>2</sup> and a quality factor of 52 at 10 kHz. The optimized films with thickness of 30 nm exhibit a leakage current density of 7 ldr 10<sup>-9</sup> A/cm<sup>2</sup> at 2 V and a breakdown strength of 3.2 MV/cm, and, therefore, meet the requirements of the current International Roadmap for Semiconductors.
IEEE Transactions on Electron Devices 09/2008; · 2.32 Impact Factor
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R. Sorge,
A. Fischer,
K.-E. Ehwald,
R. Barth,
P. Ostrovsky,
R. Pliquett,
K. Schulz,
D. Bolze,
P. Schley,
D. Schmidt,
H.-E. Wulf,
H. Grutzediek,
J. Scheerer,
P. Hartmetz
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ABSTRACT: We demonstrate the integration of a low-cost, high-voltage complementary LDMOS module with BVdss of -71V and 83V for the PLDMOS and the NLDMOS, respectively, into an advanced industrial 0.25 mum SiGe:C BICMOS process. The essential deep N-well for the high voltage PLDMOS is formed by a single 6MeV P implantation step. BVdss*ft of the NLDMOS accomplishes record values > 900 VGHz.
Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE Topical Meeting on; 02/2008
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Ch. Wenger,
G. Lippert, R. Sorge,
T. Schroeder,
A.U. Mane,
G. Lupina,
J. Dabrowski,
P. Zaumseil,
X. Fan,
L. Oberbeck,
U. Schroeder,
H.-J. MussigMussig
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ABSTRACT: The electrical characteristics of layered Al<sub>2</sub>O<sub>3 </sub>/Pr<sub>2</sub>O<sub>3</sub>/Al<sub>2</sub>O<sub>3</sub> metal-insulator-metal (MIM) capacitors for RF device applications are presented for the first time. This advanced dielectric layer system 4-nm Al<sub>2</sub>O<sub>3</sub>/8-nm Pr<sub>2</sub>O<sub>3</sub>/4-nm Al<sub>2</sub>O<sub>3</sub> shows a high capacitance density of 5.7 fF/mum<sup>2</sup>, a low leakage current density of 5times10<sup>-9 </sup> A/cm<sup>2</sup> at 1 V, and an excellent dielectric loss behavior over the studied frequency range
IEEE Transactions on Electron Devices 09/2006; · 2.32 Impact Factor
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ABSTRACT: In this paper, we present a modular and reliable complementary RF LDMOS (laterally diffused MOS) architecture fully compatible with a 0.13 mum CMOS platform. We demonstrate BV<sub>DS</sub>*f<sub>T</sub> values up to 560 and 210 GHzV, respectively, for N- and PLDMOS transistors. A major advantage of the proposed process flow is that the drift region of N- and PLDMOS transistors can be independently optimized for different BV<sub>DS</sub>without affecting the V<sub>T</sub>
Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on; 07/2006
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ABSTRACT: The performance of layered Pr<sub>2</sub>Ti<sub>2</sub>O<sub>7</sub>/SiO<sub>2</sub> MIM capacitors for mixed-signal and RF device applications is presented for the first time. A capacitance density of 3.2 fF/μm<sup>2</sup> with a very low leakage parameter of 5 fA/pFV and quadratic voltage capacitance coefficient of -100 ppm/V<sup>2</sup> was achieved. The extrapolated operating voltage for 10 years lifetime is 3 V.
Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on; 02/2006
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ABSTRACT: Pr and La oxide thin films were investigated in the context of their application as high- k dielectrics in complementary metal oxide technology. The films were deposited by molecular beam epitaxy on bare and TiN-covered Si(001). The influence of growth and post-deposition annealing on the composition and electrical parameters was studied. We observed Si penetration from bare Si(001) into the growing film. Based on the results of capacitance–voltage measurements and ab initio calculations, we conclude that Si is a source of defects responsible for leakage currents.
Applied Physics Letters 02/2005; · 3.84 Impact Factor
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ABSTRACT: We report a novel effective method for a comprehensive characterization of gate controlled diodes within an end of line CMOS process monitoring. The described technique is based on the simultaneous measurement of the gate current, the high frequency gate capacitance, and the drain current. It enables a rapid self-consistent determination of all relevant interface and near surface MOS parameters. In contrast to approaches described in the literature, the new method does not rely on the assumption of homogeneously doped samples. The practically relevant case of a doping profile in the near-surface device region is taken into account at the parameter extraction.
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European; 10/2004
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K.E. Ehwald,
A. Fischer,
F. Fuernhammer,
W. Winkler,
B. Senapati,
R. Barth,
D. Bolze,
B. Heinemann,
D. Knoll,
H. Ruecker,
D. Schmidt,
I. Shevchenko, R. Sorge,
H.-E. Wulf
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ABSTRACT: The integration of RF n-and p-LDMOS transistors into a CMOS or BiCMOS platform allows the use of complementary circuit techniques and enables efficient solutions for linear RF power amplifiers, power switches, DC/DC converters and high voltage IO circuits. We demonstrate the modular integration of high performance n-LDMOS devices and a record p-LDMOS transistor into a low-cost 0.25 μm SiGe:C RF-BiCMOS technology. In addition to n-LDMOS transistors on a p-substrate with breakdown voltages near 30 V, isolated n-LDMOS- and p-LDMOS transistors can be manufactured on the same wafer and achieve breakdown voltages of 11.5 V and 13.5 V and f<sub>T</sub>/f<sub>max</sub> values of 23/48 GHz or 13/30 GHz, respectively.
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European; 10/2004
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Solid-State Device Research Conference, 2000. Proceeding of the 30th European; 10/2000
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Solid-State Device Research Conference, 1998. Proceeding of the 28th European; 10/1998
