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T. Nirschl,
St. Henzler,
J. Fischer,
A. Bargagli-Stoffi,
M. Fulde,
M. Sterkel,
P. Teichmann,
U. Schaper,
J. Einfeld,
C. Linnenbank, [......], R. Heinrich,
N. Ostermayr,
A. Olbrich,
B. Dobler,
E. Ruderer,
R. Kakoschke,
K. Schrufert,
G. Georgakos,
W. Hansch,
D. Schmitt-Landsiedel
[show abstract]
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ABSTRACT: The tunneling field effect transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550μA/μm which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a system-on-a-chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68μm<sup>2</sup> 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
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Th. Nirschl,
P.-F. Wang,
C. Weber,
J. Sedlmeir, R. Heinrich,
R. Kakoschke,
K. Schrufer,
J. Holz,
C. Pacha,
T. Schulz,
M. Ostermayr,
A. Olbrich,
G. Georgakos,
E. Ruderer,
W. Hansch,
D. Schmitt-Landsiedel
[show abstract]
[hide abstract]
ABSTRACT: This work presents tunneling field effect transistors (TFET) fabricated with 130nm and 90nm process flows. Good performance of the TFET is achieved. A novel mixed TFET/CMOS (TCMOS) logic family exhibits the advantages with respect to power consumption. For the first time experimental results are presented for a TCMOS ring-oscillator based on a p-channel MOSFET and n-channel TFET. The benefits of the TFET used in analog circuits are outlined.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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C.G. Linnenbank,
W. Weber,
U. Kollmer,
B. Holzapfl,
S. Sauter,
U. Schaper,
R. Brederlow,
S. Cyrusian,
S. Kessel, R. Heinrich,
E. Hoefig,
G. Knoblinger,
A. Hesener,
R. Thewes
Solid-State Device Research Conference, 1998. Proceeding of the 28th European; 10/1998
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Th. Nirschl,
St. Henzler,
J. Fischer,
M. Fulde,
A. Bargagli-Stoffi,
M. Sterkel,
J. Sedlmeir,
C. Weber, R. Heinrich,
U. Schaper,
J. Einfeld,
R. Neubert,
U. Feldmann,
K. Stahrenberg,
E. Ruderer,
G. Georgakos,
A. Huber,
R. Kakoschke,
W. Hansch,
D. Schmitt-Landsiedel
[show abstract]
[hide abstract]
ABSTRACT: The scaling properties of the tunneling field effect transistor (TFET) are shown using standard 130 nm, 90 nm, and 65 nm CMOS process flows. For the different technology nodes the temperature dependence is presented. The device characteristic does not show degradation after a combined voltage and temperature cycle. It is shown that the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET. Experimental and simulation results are presented for mixed MOSFET/TFET circuits. The usage of the TFET does not cause delay degradation. The static power consumption and signal integrity are improved compared to the CMOS realization.
Solid-State Electronics.
