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R. Jansen,
S. Stoffels,
X. Rottenberg,
Y. Zhang,
J. de Coster,
S. Donnay,
S. Severi,
J. Borremans,
M. Lofrano,
G. van der Plas, P. Verheyen,
W. de Raedt,
H.A.C. Tilmans
[show abstract]
[hide abstract]
ABSTRACT: This paper reports on an optimal support anchoring for bar-type BAW resonators. We demonstrate both theoretically and experimentally the implementation of long (in terms of acoustic wavelength) T-supports without compromising neither on the Q-factor nor on the electromechanical (pull-in) stability of the resonator. Compared to the more common straight supports, these long T-supports provide rigidity for displacements in one direction combined with low stiffness in the other two directions, thus offering more freedom in the structural design, as well as potential for thermal “manipulation”, e.g., insulation.
Micro Electro Mechanical Systems (MEMS), 2011 IEEE 24th International Conference on; 02/2011
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N. Horiguchi,
B. Parvais,
T. Chiarella,
N. Collaert,
A. Veloso,
R. Rooyackers, P. Verheyen,
L. Witters,
A. Redolfi,
A. De Keersgieter,
S. Brus,
G. Zschaetzsch,
M. Ercken,
E. Altamirano,
S. Locorotondo,
M. Demand,
M. Jurczak,
W. Vandervorst,
T. Hoffmann,
S. Biesemans
[show abstract]
[hide abstract]
ABSTRACT: FinFET is a promising device structure for scaled CMOS logic/memory applications in 22nm technology and beyond, thanks to
its good short channel effect (SCE) controllability and its small variability. Scaled SRAM and analog circuit are promising
candidates for finFET applications and some demonstrations for them are already reported. On the other hand, for finFETs production,
quite a lot of process challenges are required due to difficult fin/gate patterning in the 3D structure, conformal doping
to fin and high access resistance in extremely thin body, etc. The fin/gate patterning can be improved by optimization of
patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure
in finFETs. High access resistance is reduced by junction optimization and strain boaster technique.
12/2010: pages 141-153;
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[show abstract]
[hide abstract]
ABSTRACT: The purpose of this paper is to study the impact of the different post-epi process steps on the stress behavior of epitaxially grown Si<sub>1-x</sub>-Ge<sub>x</sub> layers on Si substrates and the subsequent defectivity and device leakage. Stress measurements were performed by the in-line monitoring laser reflectance method to further investigate the intrinsic film stress dependence on the ion implantation conditions (atom size, depth of the implant, and dose) and the laser scan energy beam conditions during dopant activation (temperature, dwell time, and power). Moreover, the role of the millisecond laser anneal conditions on the area leakage current of embedded SiGe source/drain junctions is discussed. The analysis is complemented with structural characterization based on Nomarski microscopy.
IEEE Transactions on Semiconductor Manufacturing 12/2010; · 0.72 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: We demonstrate a polarization rotator fabricated using a 4 etch-step CMOS-compatible process including layer depositions on a silicon-on-insulator wafer by means of 193nm deep UV lithography. The measured polarization rotation efficiency is at least -0.5dB over a wavelength range of 80nm around 1550nm.
Group IV Photonics (GFP), 2010 7th IEEE International Conference on; 10/2010
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V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
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V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
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V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
-
V. Machkaoutsan, P. Verheyen,
M. Bauer,
Y. Zhang,
S. Koelling,
A. Franquet,
K. Vanormelingen,
R. Loo,
C. Kim,
A. Lauwers,
N. Horiguchi,
C. Kerner,
T. Hoffmann,
E. Granneman,
W. Vandervorst,
P. Absil,
S. Thomas
[show abstract]
[hide abstract]
ABSTRACT: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si"1"-"xC"x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750^oC and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si"1"-"xC"x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.
Microelectronic Engineering 01/2010; 87(3). · 1.56 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.
IEEE Transactions on Electron Devices 09/2009; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: The purpose of this paper is to evaluate the impact of process-induced stress on the generation current of fully strained Si<sub>1-</sub> x Ge x source/drain junctions. The Ge content of the compressively strained SiGe epitaxial layer plays a key role in the tensile stress levels present in the underlying Si substrate. Current-voltage ( I - V ) measurements were employed to further investigate the leakage current enhancement due to the stress-induced bandgap narrowing in the Si depletion region, when no extended defects are formed. An empirical approach is proposed to describe the Ge content dependence of the bandgap-shrinkage-induced leakage current. An increase of the intrinsic carrier concentration as a function of the stress mismatch is observed. Moreover, the role of the epilayer thickness in the generation current is also discussed.
IEEE Transactions on Electron Devices 08/2009; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: This paper evaluates the impact of the local electric field on the leakage current of strained Si1−xGex source/drain junctions. The difference in the SiGe and Si lattice constants creates a biaxial in-plane compressive stress in the epilayer and a tensile expansion on the top of the underlying silicon substrate. Current-voltage (I-V) and capacitance-voltage (C-V) measurements were employed to further investigate the stress-induced leakage current when field-assisted mechanisms such as trap-assisted-tunneling and band-to-band-tunneling are dominant, owing to the presence of high electric fields in the highly doped silicon depletion region.
Applied Physics Letters 06/2009; 94(23):233507-233507-3. · 3.84 Impact Factor
