C. O. Chui

Publications (1)0 Total impact

• Chapter: Germanium Nanodevices and Technology

  C. O. Chui, K. C. Saraswat
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  ABSTRACT: It is believed that below the 65 nm node although conventional bulk CMOS can be scaled, it will be without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65 nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. One such promising channel material is Ge due to its higher source injection velocity. However, the lack of a sufficiently stable gate dielectric and prior knowledge of doping Ge challenged the demonstration of a MOSFET device. In this chapter, we review various advanced Ge MOS device technologies on nanoscale gate stack, shallow junction, and low thermal budget integration process, which together have enabled functional metal-gated Ge MOSFETs with high-κ dielectric for the first time.
  12/2007: pages 293-313;