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ABSTRACT: In this study, commercial 512 Mb Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) modules from three progressive technologies - 130 nm, 110 nm and 90 nm - were selected for experimentation to investigate degradation trends as a function of scaling. High temperature, high voltage accelerated stress testing was performed to characterize DRAM reliability and failure rates. Retention time degradation over time as a function of stress was also studied. For each technology generation, two distinct soft error populations were observed: Tail Distribution, characterized by randomly distributed weak bits with Weibull slope =1, and Main Distribution with Weibull slope greater than 1. Retention time was found to degrade exponentially with time. Analysis reveals multiple failure mechanisms are involved in retention tim e degradation. Activation energy was found to change with stress temperature for all three technologies. There are several observations with regard to scaling effects on DRAM reliability. First, the smaller the technology, the larger the operating current increases in percentage after high temperature, high voltage accelerated stress. Second, cell retention time variation decreases as technology scales down. Third, 90 nm DRAM has the largest soft-error failure rate among three technologies under equivalent stress, 110 nm DRAM has better reliability performance than 130nm at 55°C and 75°C, and 130nm DRAM is the best at 125°C. Studies con tinue into the scaling effects on reliability of progressive DRAM technologies.
Reliability and Maintainability Symposium (RAMS), 2011 Proceedings - Annual; 02/2011
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ABSTRACT: On-die measurements of V <sub>DD</sub> and V <sub>SS</sub> voltages inside a 90-nm VLSI technology chip are presented. The results show local fluctuations in the V <sub>DD</sub> and V <sub>SS</sub> voltages with amplitudes that can reach, in severe cases, more than 10% of V <sub>DD</sub>. These fluctuations can distort analog signals, cause immediate logic faults, and also aggravate other reliability wear-out mechanisms. Both measurements and simulations predict the aggravation of this phenomenon for future technologies.
IEEE Transactions on Device and Materials Reliability 10/2009; · 1.54 Impact Factor
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ABSTRACT: In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.
IEEE Transactions on Device and Materials Reliability 10/2009; · 1.54 Impact Factor
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ABSTRACT: Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range reliability of dielectric layers in SiC-based high-power devices. Despite the extensive research on TDDB of SiO<sub>2</sub> layers on Si, there is a lack of high-quality statistical TDDB data of SiO<sub>2</sub> layers on SiC. This paper presents comprehensive TDDB data of 4H-SiC capacitors with a SiO<sub>2</sub> gate insulator collected over a wide range of electric fields and temperatures. The results show that at low fields, the electric field acceleration parameter is between 2.07 and 3.22 cm/MV. At fields higher than 8.5 MV/cm, the electric field acceleration parameter is about 4.6 cm/MV, indicating a different failure mechanism under high electric field stress. Thus, lifetime extrapolation must be based on failure data collected below 8.5 MV/cm. Temperature acceleration follows the Arrhenius model with activation energy of about 1 eV, similar to thick SiO<sub>2</sub> layers on Si. Based on these experimental data, we propose an accurate model for lifetime assessment of 4H-SiC MOS devices considering electric field and temperature acceleration, area, and failure rate percentile scaling. It is also demonstrated that temperatures as high as 365<sup>deg</sup>C can be used to accelerate TDDB of SiC devices at the wafer level.
IEEE Transactions on Device and Materials Reliability 01/2009; · 1.54 Impact Factor
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ABSTRACT: NBTI has been extensively studied to understand physics of degradation in recent years. However, little has been done to find out the lifetime distributions of NBTI at both transistor and product level, which are important in reliability prediction and improvement. In this paper, Monte-Carlo simulation is carried out to study the NBTI lifetime distribution at transistor level. Lognormal distribution is found to have the best fit. Product level NBTI lifetime distribution is studied through rare event simulation. Result shows that Weibull distribution has a better fit than lognormal distribution at product level. Acceleration test result of 90 nm SRAM cache NBTI degradation is compared with the simulation results and a good agreement is observed.
Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International; 11/2008
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ABSTRACT: For the first time, a high speed flash ADC is developed for reliability analysis and simulation of analogue and mix-signal circuit. All the three failure mechanisms (NBTI, HCI, TDDB) are quantified with degradation models. The result shows that pMOS degradation especially NBTI is the most detrimental failure mechanism for the normal operation of high speed ADC, which leads to the fault output. Based on the analysis of the reliability-critical parts, reliability improvement approaches are suggested for the reliable design.
Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International; 11/2008
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ABSTRACT: Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO<sub>2</sub> and NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of the instability underestimated by dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Postoxidation annealing in NO was found to passivate the oxide traps and dramatically reduce the instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO<sub>2</sub> interface is proposed.
IEEE Transactions on Electron Devices 09/2008; · 2.32 Impact Factor
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ABSTRACT: The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.
IEEE Transactions on Device and Materials Reliability 04/2008; · 1.54 Impact Factor
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ABSTRACT: For ultrathin gate oxide, soft breakdown (SBD) has been extensively studied but not fully integrated into circuit reliability simulation. Using a 6T SRAM cell as a generic circuit example, the time-dependent SBD was incorporated into circuit degradation analysis based on the exponential defect current growth model [1]. SRAM cell stability degradation due to individual failure mechanism was characterized. Multiple failure mechanisms degradation effect was also studied in regard of SRAM cell operation. Simulation results showed that gate oxide SBD is the dominating failure mechanism which causes SRAM stability and operation degradation, NBTI and HCI have much less effect.
Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International; 11/2007
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M. Gurfinkel,
Jinwoo Kim,
S. Potbhare,
H.D. Xiong,
K.P. Cheung,
J. Suehle, J.B. Bernstein,
Y. Shapira,
A.J. Lelis,
D. Habersat,
N. Goldsman
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ABSTRACT: The results show that devices with "as grown" SiO<sub>2</sub> have a much higher density of bulk oxide traps than devices after post oxidation annealing in NO environment. The amount of oxide fixed charge is clearly not affected by the annealing process. Devices fabricated on ion-implanted channels exhibit only a small increase in the bulk oxide trap density and the fixed charge. On the other hand, the density of the interface traps is increased dramatically. This suggests that the damage due to the ion-implantation process is mainly interfacial. In contrast to Si devices, this ion-implantation damage is not completely repaired, even after annealing.
Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International; 11/2007
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ABSTRACT: An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO <sub>2</sub>/HfO<sub>2</sub> gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO<sub>2</sub> layer and HfO<sub>2</sub>/SiO<sub>2</sub> interface region. The trap density in the SiO<sub>2</sub> layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO<sub>2</sub> layer
IEEE Transactions on Electron Devices 07/2007; · 2.32 Impact Factor
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ABSTRACT: One of the most important issues that limits the performance and reliability of SiC power MOSFETs is the threshold voltage and drain current instability under normal operation conditions. This phenomenon has been recently studied using conventional dc measurements. In this work, the authors studied the threshold voltage and drain current instability in state-of-the-art 4H-SiC MOSFETs using fast I-V measurements. Fast I-V measurements reveal the full extent of the instability, underestimated by the dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Post oxidation annealing in NO was found to passivate the oxide traps and dramatically reduce instability. A physical model involving fast transient charge trapping and de-trapping at and near the SiC/SiO<sub>2</sub> interface is proposed.
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
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ABSTRACT: High-K dielectric gate stack MOSFETs have been characterized by separating the transversal and lateral electric field contributions to the substrate current. The results show that at low gate biases the substrate current is dominated by a trap-assisted tunneling component denoted by gate induced drain leakage (GIDL) current, which is not observed in conventional SiO<sub>2</sub>devices. Ultra-fast substrate current measurements rule out transient charging of the gate oxide as the cause of this component. A physical model of the observed substrate current dependence is proposed
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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IEEE Transactions on Electron Devices 01/2007; 54(6):1338-1345. · 2.32 Impact Factor
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ABSTRACT: As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s)
Integrated Reliability Workshop Final Report, 2006 IEEE International; 10/2006
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ABSTRACT: One of the most important issues that limits the performance and reliability of SiC power MOSFETs is the threshold voltage instability under normal operation conditions. This phenomenon has been recently studied using dc sweep measurements. In this work, we studied the threshold voltage instability using fast I-V measurements. The results show that under positive bias, V<sub>TH</sub> shifts to more positive values, while it shifts to more negative values under negative bias. Fast I-V measurements reveal the full extent of the V<sub>TH</sub> instability, underestimated by the dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. A physical model involving fast transient charge trapping and de-trapping at and near the SiC/SiO<sub>2</sub> interface is proposed
Integrated Reliability Workshop Final Report, 2006 IEEE International; 10/2006
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ABSTRACT: In this paper, we study temperature and voltage acceleration of semiconductor device with multiple intrinsic failure mechanisms involved: hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI). Simulation shows that system activation energy and voltage acceleration parameter depend on stress temperature and voltage. A modified Arrhenius relationship is proposed to model the temperature dependence of device lifetime at given voltage. A modified exponential model is also proposed to model the voltage dependence of device lifetime at given temperature
Integrated Reliability Workshop Final Report, 2006 IEEE International; 10/2006
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ABSTRACT: Based on some new accelerated lifetime models and failure equivalent circuit modeling techniques for the common semiconductor wear out mechanisms, simulation program with integrated circuit emphasis (SPICE) can be used to characterize CMOS VLSI circuit failure behaviors and perform reliability simulation. This paper used a simple SRAM circuit as an example to demonstrate how to apply SPICE to circuit reliability modeling, simulation, analysis, and design. The SRAM circuit, implemented with a commercial 0.25-mum technology, consists of functional blocks of 1-bit six-transistor cell, precharge, read/write control, and sense amplifier. The SRAM operation sequence of "write 0, read 0, write 1, read 1" was first simulated in SPICE to obtain the terminal voltage and current stress profiles of each transistor. Then, normalized lifetimes of all transistors in terms of each failure mechanism were calculated with the corresponding accelerated lifetime models. These lifetime values were sorted to single out the most damaged transistors. Finally, the selected transistors were substituted with failure equivalent circuit models, and SPICE simulations were performed again to characterize the circuit performance, functionality, and failure behaviors. The simulation shows that the 0.25-mum technology, hot-carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) had significant effects on SRAM-cell stability and voltage-transfer characteristics, while negative bias temperature instability (NBTI) mainly degraded the cell transition speed when the cell state flipped. This illustrative SRAM simulation work proves that, with SPICE and the failure equivalent circuit models, circuit designers can better understand the damage effects of HCI/TDDB/NBTI on the circuit operation, quickly estimate the circuit lifetime, make appropriate performance/reliability tradeoffs, and formulate practical design guidelines to improve the circuit reliability
IEEE Transactions on Device and Materials Reliability 07/2006; · 1.54 Impact Factor
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ABSTRACT: CMOS very large scale integration (VLSI) circuit reliability modeling and simulation have attracted an intense research interest in the last two decades, and as a result, almost all IC reliability simulation tools now try to incrementally characterize the wearout mechanisms of aged devices in iterative ways. These tools are able to accurately simulate the device's wearout process and predict its impact on the circuit performance. Nevertheless, an excessive simulation time, a tedious device testing work, and a complex parameter extraction process often limit the popularity of these tools in the product design and fabrication stages. In this paper, a new simulation program with integrated circuits emphasis (SPICE) reliability simulation method is developed, which shifts the focus of the reliability analysis from the device wearout to the circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models have been proposed for the most common silicon intrinsic wearout mechanisms, including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability. The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current stress profiles. Then, the corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, the SPICE simulation is performed again to check the circuit functionality and analyze the impact of the device wearout on the circuit operation. Device individual wearout effect is lumped into a very limited number of SPICE circuit elements within each failure equivalent circuit model, and the circuit performance degradation and functionality are determined by the magnitude of these additional circuit elements. In this new method, it is unnecessary to perform a large number of small-step iterative SPICE simulation process as other tools required t-
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o obtain the accuracy. Therefore, the simulation time is obviously shortened. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE parameters, need to be accurately characterized at each interim wearout process. Thus, the device testing and parameter extraction work are also significantly simplified. These advantages will allow the circuit designers to perform a quick and efficient circuit reliability analysis and to develop practical guidelines for reliable electronic designs
IEEE Transactions on Device and Materials Reliability 07/2006; · 1.54 Impact Factor
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Applied Physics Letters 01/2006; 88(15):152907-152907. · 3.84 Impact Factor
