-
[show abstract]
[hide abstract]
ABSTRACT: We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies
of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and Monte Carlo methods to
show the long channel dependencies of these effects on gate fields, doping levels, extrinsic charges, and homogeneous driving
fields. Our model predicts the reduced effect of wafer orientation on short channel linear and saturation current drives due
to weak gate confinement, high carrier density, high stress, and high driving field prevalent in scaled devices. This reduces
NMOS (110) wafer orientation loss compared to (100), while keeping PMOS (110) gains over (100) surface orientation in current
drives in 〈110〉 channels, consistent with data.
Journal of Computational Electronics 04/2012; 8(2):110-123. · 1.21 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Simulation approaches used in Intel to evaluate the applicability of new devices and materials for future microprocessor technologies are reviewed. Examples discussed include the evaluation of highly stressed materials, III -V HEMT devices, and carbon nanoribbons. The techniques employed are similar to those used in the research community, but focused on efficient evaluation within a versatile infrastructure that works for both development and research.
Computational Electronics, 2009. IWCE '09. 13th International Workshop on; 06/2009
-
[show abstract]
[hide abstract]
ABSTRACT: A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 "wings," where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility
IEEE Transactions on Electron Devices 09/2006; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: This paper describes the fabrication and performance of uniaxial strained silicon CMOS transistors with NiSi metal gate electrodes and ultra-thin 1.2nm gate oxide. This work offers the first comprehensive evaluation of Si CMOS devices integrating NiSi metal gate (FUSI) process with highly strained Si channels. Performance gains from FUSI gate stack and uniaxial strained Si channels are demonstrated to be fully additive and enable record high drive currents - NMOS l<sub>DSAT</sub>=1.75mA/mum, PMOS I<sub>DSAT</sub>=1.06mA/mum (V<sub>DD</sub>=1.2V, I<sub>OFF</sub>=100nA/mum). These devices have the best I<sub>DSAT</sub> vs. I<sub>OFF</sub> characteristics reported to date in the industry
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
-
S.M. Cea,
M. Armstrong,
C. Auth,
T. Ghani,
M.D. Giles,
T. Hoffmann,
R. Kotlyar,
P. Matagne,
K. Mistry,
R. Nagisetty,
B. Obradovic,
R. Shaheed,
L. Shifren, M. Stettler,
S. Tyagi,
X. Wang,
C. Weber,
K. Zawadzki
[show abstract]
[hide abstract]
ABSTRACT: This paper presents an integrated approach to modeling front end stress which has been used to investigate the main sources of stress in advanced logic technologies and how they can be used to improve device performance. The approach is illustrated with the evaluation of several technologically important stress options.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
E. Wang,
P. Matagne,
L. Shifren,
B. Obradovic,
R. Kotlyar,
S. Cea,
J. He,
Z. Ma,
R. Nagisetty,
S. Tyagi, M. Stettler,
M.D. Giles
[show abstract]
[hide abstract]
ABSTRACT: We have developed a quantum anisotropic transport model for holes which, for the first time, allows mobility to be studied under both uniaxial and arbitrary stress in PMOS inversion layers. The anisotropic bandstructure of a 2D quantum gas is computed from a 6-band stress dependent k.p Hamiltonian. Our unique momentum-dependent scattering model also captures the anisotropy of scattering. A comprehensive study has been performed for uniaxial stress, biaxial stress, and their nonlinear interactions. The results are compared with device bending data and piezoresistance data, showing very good agreement.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
[show abstract]
[hide abstract]
ABSTRACT: For the first time, we show with simulation that the use of a metal gate/high-k stack offers improved mobility over polysilicon/high-k gates stacks while maintaining decreased gate leakage compared to conventional SiO<sub>2</sub> stacks, thus allowing high-performance transistor scaling to continue.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
L. Shifren,
X. Wang,
P. Matagne,
B. Obradovic,
C. Auth,
S. Cea,
T. Ghani,
J. He,
T. Hoffman,
R. Kotlyar,
Z. Ma,
K. Mistry,
R. Nagisetty,
R. Shaheed, M. Stettler,
C. Weber,
M. D. Giles
[show abstract]
[hide abstract]
ABSTRACT: Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n -type MOSFETs (NMOS) and p -type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.
Applied Physics Letters 01/2005; · 3.84 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A novel computationally efficient model for stress-modulated hole mobility, suitable for a continuum transport simulators, has been developed and implemented. The physically-based model captures bandstructure modulation due to stress, and reproduces the experimental mobility behavior over a wide range of stress, electric fields, and current directions. The model is validated and calibrated using a set of wafer bending experiments. Devices of various lengths (with built-in stress) are subjected to additional longitudinal or transverse stress from the wafer bending, for a total stress range (bending plus structural) of 700 MPa tensile to 800 MPa compressive. The overall agreement to data is found to be very good, with only a slight increase (∼10% for typical cases) in the required CPU time.
Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on; 11/2004
-
M.D. Giles,
M. Armstrong,
C. Auth,
S.M. Cea,
T. Ghani,
T. Hoffmann,
R. Kotlyar,
P. Matagne,
K. Mistry,
R. Nagisetty,
B. Obradovic,
R. Shaheed,
L. Shifren, M. Stettler,
S. Tyagi,
X. Wang,
C. Weber,
K. Zawadzki
[show abstract]
[hide abstract]
ABSTRACT: A hierarchical, model-based understanding of the key physical effects underlying stress-induced device performance gain is presented, focusing on the large gains seen for uniaxial PMOS stress conditions and the vertical stress impact on NMOS gain.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
-
[show abstract]
[hide abstract]
ABSTRACT: The technologically important question of whether the reduced density of electron states (DOS) for scattering in one-dimensional (1D) wire transport devices gives an advantage over the planar metal–oxide–semiconductor field-effect-transistor (MOSFET) for electron mobility is assessed by simulations. We self-consistently solve the Schrödinger–Poisson equations to calculate phonon-limited electron mobility in a multisubband cylindrical Si gated wire. We find that the benefit of reduced 1D DOS is offset by an increased phonon scattering rate due to increased electron–phonon wave function overlap and results in a degraded mobility in narrow wires. The applied gate bias voltage and the wire size control the transition from wire geometry to surface field-dominated confinement. The size scale for this 1D to two-dimensional (2D) transition is also found to be surprisingly small: A wire with a 75 A radius has an essentially 2D DOS and has a 2D mobility that is degraded from the planar (100) MOSFET due to the anisotropy of the inversion mobility in different Si crystallographic planes. © 2004 American Institute of Physics.
Applied Physics Letters 06/2004; 84(25):5270-5272. · 3.84 Impact Factor
-
S. Thompson,
M. Alavi,
R. Arghavani,
A. Brand,
R. Bigwood,
J. Brandenburg,
B. Crew,
V. Dubin,
M. Hussein,
P. Jacob, [......],
M. Prince,
R. Schweinfurth,
S. Sivakumar,
P. Smith, M. Stettler,
S. Tyagi,
M. Wei,
J. Xu,
S. Yang,
M. Bohr
[show abstract]
[hide abstract]
ABSTRACT: A leading edge 130 nm technology with 6 layers of Cu interconnects
and 1.3 V operation has previously been presented (Tyagi et al., 2000).
In this work, we enhance the previous technology with the following:
transistor improvements which support a 60 nm gate dimension and
increased drive current, improved 6-T SRAM device matching to allow low
power and high performance operation from 0.7 to 1.4 V, and a 5% linear
shrink to reduce the 6-T SRAM cell to 2.00 μm<sup>2</sup> while still
using 248 nm lithography. Saturation drive currents of 1.30 mA/μm for
N-channel and 0.66 mA/μm for P-channel low VT devices are the highest
reported to date. Excellent device short channel effects are obtained
for the 60 nm gate length devices as measured by the 270 mV threshold
voltage and <100 mV/V DIBL. These results have been achieved on both
200 and 300 mm wafers
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
-
[show abstract]
[hide abstract]
ABSTRACT: Summary form only given. We investigate scaling challenges and
outline device design requirements needed to support high
performance-low power planar CMOS transistor structures with physical
gate lengths (L<sub>GATE</sub>) below 50 nm. This work uses a
combination of simulation results, experimental data and critical
analysis of published data. A realistic assessment of gate oxide
thickness scaling and maximum tolerable oxide leakage is provided. We
conclude that the commonly accepted upper limit of 1 A/cm<sup>2</sup>
for gate leakage is overly pessimistic and that leakage values of up to
100 A/cm<sup>2</sup> are deemed acceptable for future logic technology
generations. Unique channel mobility and junction edge leakage
degradation mechanisms, which become prominent at 50 nm L<sub>GATE</sub>
dimensions, are highlighted using quantitative analysis. Source-drain
extension (SDE) profile design requirements to simultaneously minimize
short channel effects (SCE) and achieve low parasitic resistance for
sub-50 nm L<sub>GATE</sub> transistors are described for the first time
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
-
S. Tyagi,
M. Alavi,
R. Bigwood,
T. Bramblett,
J. Brandenburg,
W. Chen,
B. Crew,
M. Hussein,
P. Jacob,
C. Kenyon, [......],
P. Nguyen,
L. Rumaner,
R. Schweinfurth,
S. Sivakumar, M. Stettler,
S. Thompson,
B. Tufts,
J. Xu,
S. Yang,
M. Bohr
[show abstract]
[hide abstract]
ABSTRACT: A leading edge 130 nm generation logic technology with 6 layers of
dual damascene Cu interconnects is reported. Dual Vt transistors are
employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt
transistors have drive currents of 1.03 mA/μm and 0.5 mA/μm for
NMOS and PMOS respectively, while low Vt transistors have currents of
1.17 mA/μm and 0.6 mA/μm respectively. Technology design rules
allow a 6-T SRAM cell with an area of 2.45 μm<sup>2</sup>, while
array specific design rule give the densest SRAM reported to date, the
6-T cell has an area of only 2.09 μm<sup>2</sup>. Excellent yield and
performance is demonstrated on a 18 Mbit CMOS SRAM
Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
-
[show abstract]
[hide abstract]
ABSTRACT: The cumulant expansion method is proposed to solve the Boltzmann transport equation (BTE) in semiconductors. This method involves deriving a set of partial differential equations for the expansion coefficients from a Fourier transformation of the BTE. The collision terms for phonon emission and absorption scattering are obtained directly from quantum computed scattering transition rates, without invoking the relaxation time approximation. Unlike the moment expansion method used in hydrodynamic models, the cumulant expansion converges much faster when the distribution function is close to a drifted maxwellian because, for this case, only the first three cumulants are non-zero. This method also provides a way to construct an arbitrary distribution function from the computed cumulants, without being limited to a shifted maxwellian
Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on; 11/1998
-
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we investigate the scaling of source/drain
extension (SDE) depth and SDE to gate overlap for 0.1 μm and below
MOSFETs. We show for the first time that a minimum SDE to gate overlap
of 15-20 nm is needed to prevent drive current (I<sub>DSAT</sub>)
degradation. We also show for the first time that scaling SDE vertical
depths below 30-40 nm results in little to no performance benefit for
0.1 μm devices and beyond since any improvement in short channel
effects due to reduced charge sharing is offset by a large increase in
external resistance and poor gate coupling between the channel and
extensions
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on; 07/1998
