V. Khemka

Freescale Semiconductors, Inc, Austin, Texas, United States

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Publications (54)33.89 Total impact

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    ABSTRACT: This paper reports Super-Junction NLDMOS device implemented in Freescale's 0.13 μm SOI based Smart Power IC technology. This SJ device can be operated at both high and low side applications without back-gate effect. It achieves breakdown voltage of 111V and Rds.on × area of 138 mΩ.mm<sup>2</sup> with robust characteristics.
    Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on; 07/2010
  • T. Khan, V. Khemka, Ronghua Zhu, A. Bose
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    ABSTRACT: This paper presents the extremely robust and innovative dotted-channel structure which utilizes a unique approach of suppressing the parasitic bipolar to significantly improve the SOA and push the boundaries of LDMOS operation to a new realm. The structure has body contact placed through the poly-silicon gate of the standard MOSFET resulting in a hole (h+) collection site in front of the source which in turn shunts the base emitter path of the parasitic bipolar.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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    ABSTRACT: We report on the experimental demonstration of revolutionary 5.5 V zero-channel power MOSFETs with record low specific on-resistance of 1.0 mOmegaldrmm2 and Figure of Merit (RontimesQg) of 8.4 mOmegaldrnC with optimized metal layout. This novel device also shows good Hot Carrier Injection (HCI) immunity.
    01/2009;
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    ABSTRACT: In this paper, a unique Combined Lateral Vertical RESURF (CLAVER) LDMOS structure is proposed for breakthrough performance. The structure uses a secondary RESURF design to terminate in the vertical direction to yield a much improved performance trade-off. The proposed device uses standard process steps available in integrated technology platforms to give a breakdown as high as 150 V with ground-breaking on-state resistance of 159 mOhm-mm2.
    01/2009;
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    ABSTRACT: In this paper, a novel Schottky diode structure based on the superjunction concept is proposed. The concept is based on 2-carrier current conduction and utilizes both P and N columns for current conduction. The proposed device utilized the P and N superjunction columns to achieve high breakdown with low leakage current.
    01/2009;
  • T. Khan, V. Khemka, Ronghua Zhu
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    ABSTRACT: In this paper, a novel structure based on the Floating RESURF LDMOSFET is proposed for enhanced off-state blocking capability. The new structure facilitates the implementation of FRESURF concept in thicker epi technologies for higher voltage tiers. An additional floating island is introduced, sandwiched between the standard drift region and heavily doped buried layer, which makes the Incremental FRESURF action feasible. Best case BV<sub>DSS</sub> of 130V with R<sub>DS,ON</sub> of 1.6mω-cm<sup>2</sup> has been experimentally realized on a 0.13μm, SOI based smart power technology which is a significant improvement as compared to other state of the art integrated high voltage technologies
    Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
  • V. Khemka, Ronghua Zhu, T. Khan, A. Bose
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    ABSTRACT: In this paper we demonstrate and evaluate the impact of deep sub-micron design rules on the performance of RESURF LDMOSFET devices in smart power technologies. It is observed that the device parameters such as breakdown voltage, specific on-resistance, safe operating area (SOA) depend significantly on the width of the drain active opening. Simply reducing the active opening width to minimum allowed by the technology design rules may not always yield best device performance. In deep sub-micron smart power technologies where one or two implants are often utilized to construct variety of devices for multiple voltage-tiers, this can provide an effective tool for device performance
    Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on; 06/2007
  • R Zhu, V. Khemka, A. Bose
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    ABSTRACT: Power device safe operating area (SOA), ESD immunity and energy capability are of particular importance for smart power IC technologies used in harsh applications. This paper discusses some of the powerful drain and body engineering techniques used in Freescale's advanced smart power technology to provide robust device characteristics.
    Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on; 06/2007
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    ABSTRACT: This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart-power technology. The impact of logic ground isolation from the substrate and the presence p<sup>+</sup> and n<sup>+</sup> buried layers below the logic wells is quantified. Four different types of structures have been studied and it is demonstrated that certain ion-implantation layers that are inherently available in a standard deep submicron smart-power process due to medium and high-voltage requirements can be effectively utilized to optimize and improve the latchup performance of standard CMOS.
    IEEE Transactions on Device and Materials Reliability 04/2007; · 1.52 Impact Factor
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    ABSTRACT: This paper discusses substrate majority carrier conduction and prevention for an n-type lateral double diffused MOSFET (NLDMOSFET) device in Smart Power IC technologies. Substrate majority carrier current poses severe electrical and thermal stress for NLDMOSFET devices and causes many system integration issues for advanced Smart Power IC technologies. A single- and multi-iso isolated NLDMOSFET is proposed and experimentally verified to eliminate the problem. Tradeoff between device size, safe operating area (SOA), substrate current, and NLDMOSFET-device power dissipation has been studied. Detailed analysis of device SOA for conventional and isolated devices and techniques to improve the device SOA has also been provided
    IEEE Transactions on Device and Materials Reliability 10/2006; · 1.52 Impact Factor
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    ABSTRACT: A novel drift region engineered stepped-drift LDMOSFET device in Freescale's 0.25mum smart power technology is reported for the first time. The specific on-resistance of the device is 0.33 mOmegamiddotcm<sup>2</sup> at breakdown voltage of 59 V, the best reported data to date. SOA of the device has been improved up to 87% compared to its conventional counterpart
    Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on; 07/2006
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    ABSTRACT: In this paper we propose and demonstrate a novel NLDMOSFET device concept, designed for deep sub-micron smart power technologies. The proposed device is designed with a P+ current diverter in the LDMOS drain so as to create a base-collector shorted PNP bipolar transistor from the source to the drain terminal of the LDMOS. Due to the inherent gain associated with the PNP device, the proposed LDMOSFET diverts more current in to the source/body terminal during reverse current injection phase, thereby reducing the amount of current that can get injected in to the substrate. Both single and double resurf LDMOSFETs have been investigated and dramatic improvement in substrate injection suppression is observed with no loss in breakdown voltage. Proposed devices also demonstrated significantly enhanced robustness and safe operating area (SOA)
    Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on; 07/2006
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    ABSTRACT: This paper discusses substrate majority carrier conduction and prevention for a NLDMOS device in smart power technologies. A multi-iso isolated NLDMOS is proposed and experimentally verified to eliminate the problem. Trade-off between device size, safe operating area, substrate current and NLDMOS device power dissipation has been studied
    Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International; 04/2006
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    ABSTRACT: This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart power technology. The impact of logic ground isolation from the substrate and the presence of P+ and N+ buried layers below the logic wells is quantified
    Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International; 04/2006
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    ABSTRACT: In this paper we propose and demonstrate a novel Schottky device concept, which is capable of achieving ultra low leakage current with high breakdown voltage. The proposed Schottky diode is conceived and designed with a lateral configuration for deep sub-micron smart power technologies but can also be designed in a vertical discrete configuration. A combination of depletion mode MOSFET and n or p-type Schottky junctions are utilized to create hybrid MOS Schottky (HMS) diode where the high reverse bias voltage is blocked by the MOSFET. The device is first demonstrated in a circuit configuration with discrete Schottky diode and a MOSFET. Subsequently, low separate monolithic integrated versions of the diode are proposed and realized. The integrated version of the diode achieved near-ideal characteristics with an ideality factor, n of 1.04 and a barrier height o<sub>B</sub> of 0.64eV.
    Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on; 06/2005
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    ABSTRACT: In this letter, we propose and demonstrate a novel device based on a floating reduced surface field (FRESURF) concept which allows the realization of significantly higher breakdown voltage in a thin epitaxy-based power IC technology. The newly proposed device with the floating buried layer pulled back from the source side is able to realize an enhanced breakdown voltage (BV<sub>dss</sub>) without degrading the specific on-resistance (R<sub>dson</sub>A). BV<sub>dss</sub>-R<sub>dson</sub>A values like 47 V-0.28 mΩ·cm<sup>2</sup> or 93 V-0.82 mΩ·cm<sup>2</sup> have been realized with a conventional power IC technology without any added process complexity.
    IEEE Electron Device Letters 01/2005; · 2.79 Impact Factor
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    ABSTRACT: This letter reports a novel technique to isolate thermal and electrical failure mechanisms in a power LDMOSFET device by deactivating the parasitic bipolar transistor while maintaining the MOS gate control. It is shown that the energy capability of the device remains constant as a function of the drain voltage in the event of a purely thermal failure, whereas the standard device shows a decrease in energy capability indicating electrothermal coupling. Nevertheless, the standard device energy capability is close to that obtained in the case of pure thermal failure, indicating that the thermal phenomenon dominates in determining the device failure and that electrical effects, though present, only minutely influence the device failure.
    IEEE Electron Device Letters 11/2004; · 2.79 Impact Factor
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    ABSTRACT: In this paper, simultaneous optimisation of 4.5-5.5 V N and PMOS devices, 20-30 V NLDMOS, and NPN and PNP bipolar devices in a 0.25 μm smart power technology for portable wireless and consumer applications is discussed. With the addition of two designated wells, ultra-low resistance N and PMOS devices with good analogue characteristics, best in class 30 V NLDMOS, and integrated high performance NPN and PNP bipolar devices are demonstrated. Practical implementation of a high voltage, isolated diode using an existing device is also discussed and demonstrated.
    IEE Proceedings - Circuits Devices and Systems 07/2004; · 0.36 Impact Factor
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    ABSTRACT: Temperature distribution inside a large-area reduced-surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) is studied with the help of experiments and theoretical modeling. Diode sensors are integrated inside a large area device to map the temperature as a function of distance. Temperature distribution is then optimized with the help of distribution of power across the device. Several layout techniques are presented and experimentally demonstrated for realizing this power distribution. It is shown that power applied to the device can be graded across the device by varying the saturation drain current in different parts of the device. Conventional devices with uniform power distribution achieved a critical failure temperature of 650 K at a drain to source voltage of about 40 V with a corresponding energy of 160 mJ/mm<sup>2</sup>, whereas devices with graded power distribution achieved a critical failure temperature of about 560 K, even though the total energy capability of the device increases to 192 mJ/mm<sup>2</sup>. It is also shown that the destruction point in the device shifts from the center of the device to the periphery. It is observed that as the power is graded across the device there is a counter balancing effect created by the increased impact ionization around the periphery of the device, which limits the energy capability improvement to be gained. Reducing the impact ionization rate by operating the device at V<sub>ds</sub>=30 V showed an increase in critical temperature for the graded distribution device to 610 K.
    IEEE Transactions on Electron Devices 07/2004; · 2.06 Impact Factor
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    ABSTRACT: In this paper, we propose and demonstrate a novel device concept, which is an extension of the conventional reduced surface field (RESURF) concept. A heavily doped n-type floating region is introduced in the conventional lateral DMOSFET (LDMOS) device structure which allows the breakdown capability of the device to be increased significantly while at the same time making it high-side capable. This floating RESURF (FRESURF) device concept allows the realization of significantly higher breakdown voltage in a thin epitaxy based power IC technology. Several different LDMOS type device structures based on the FRESURF concept are proposed, simulated and experimentally demonstrated. Breakthrough BV<sub>dss</sub>-R<sub>dson</sub>A trade-off has been realized using this device, which can be fabricated in a conventional power IC technology without any added process complexity. BV<sub>dss</sub>-R<sub>dson</sub>A figures like 47 V 0.28mΩ.cm<sup>2</sup> or 93 V - 0.82 mΩ.cm<sup>2</sup> have been realized, which are best reported figures in the industry for this class of power device and on-par with some of the figures achieved using more complicated superjunction technology.
    Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on; 06/2004