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Publications (2)0 Total impact

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    ABSTRACT: An I/O transceiver for scalable multiprocessor systems with 1.25 Gb/s parallel bandwidth and 7.7 ns latency performs as a plesiochronous link and compensates for skin-effect cable loss and inter-wiring skew across 20 m cable connections. Phase-interpolator-based clock recovery integrates multiple I/O links that can tolerate slight differences in frequencies between incoming and internal reference clocks. A differential partial-response detection (DPRD) receiver ensures low latency equalization for skin-effect cable loss of up to 10 dB. The receivers are equipped with deskew circuitry to tolerate up to 6.4 ns inter-wiring skew for 20 data bits. The data rate, driver output level, and receiver clock phase are adjusted automatically by a logic sequencer, basic control, which maximizes data rate and minimizes power consumption without external manual adjustment, adapting from onboard PCB traces to 20 m twisted-pair cables
    Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International; 02/1999
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    ABSTRACT: A chip-to-chip signaling scheme employs partial response detection (PRD) combined with the zero-delay time delivery of a global timing reference, or global mean time (GMT). High-output-impedance drivers and higher termination resistances for signal transmission reduce driver power to the 10 mW range while maintaining a data rate of 500Mb/s. The resulting intersymbol interference (ISI) is eliminated by the PRD receivers, a type of auto-zero-comparator. Signal lines are segmented and pipelined by PRD buffers to limit the segment lengths to below Lmax=cT/2, where c is the effective velocity of signal propagation and T is the bit time. Segmentation reduces the driver power considerably
    Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International; 03/1998