R. del Rio

Publications (36)14.25 Total impact

• Article: A modem in CMOS technology for data communication on the low-voltage power line

  O Guerra, C Dominguez-Matas, S Escalera, J Garcia-Gonzalez, G Linan, R del Rio, M Delgado-Restituto, A Rodriguez-Vazquez
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  ABSTRACT: This paper presents a CMOS 0.8 mum mixed-signal half-duplex Modem ASIC for data transmission on the low-voltage power line. It includes all the analog circuitry needed for input interfacing and modulation/ demodulation (low-noise amplifier, PLL-based frequency synthesis, tunable filter banks, and decision circuitry), logic circuitry for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283muV(rms) (these are worst case values among 30 randomly-selected samples used as vehicles for detailed electrical characterization; most of the samples featured 200 muV(rms), sensitivity; bit error rate (BER) is below 0.5 x 10(-5)) at 10 kbps, and operates correctly in the whole industrial temperature range, from -45degreesC to 80degreesC, under 5% variations of the 5V supply voltage. This ASIC is now in commercial production. (C)2003 Published by Elsevier B.V.
  01/2003; 36:229-236.
• Conference Proceeding: A 2.5-V ΣΔ modulator in 0.25-μm CMOS for ADSL

  R. del Rio, F. Medeiro, J.M. de la Rosa, B. Perez-Verdu, A. Rodriguez-Vazquez
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  ABSTRACT: This paper presents a dual-quantization cascade SC ΣΔ modulator intended for A/D conversion in ADSL applications. The modulator combines a low oversampling ratio with 3-bit resolution in the last stage, to achieve 14bit@4.4MS/s (16×) and 15bit@2.2MS/s (32×) with no need of correction/calibration mechanisms. It consumes 66 mW from a single 2.5-V supply and has been implemented in 0.25-μm CMOS technology.
  Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
• Source

  Available from: csic.es

  Conference Proceeding: Analysis and experimental characterization of idle tones in 2nd-order bandpass ΣΔ modulators-a 0.8 μm CMOS switched-current case study

  J.M. de la Rosa, B. Perez-Verdu, F. Medeiro, R. del Rio, A. Rodriguez-Vazquez
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  ABSTRACT: This paper analyses the tonal behaviour of the quantization noise in 2nd-order bandpass ΣΔ modulators. The analysis previously performed for lowpass modulators is extended to the bandpass case. As a result, closed-form expressions for the frequency of the idle tones are derived for different locations of the signal center frequency. The analytical results are validated through measurements from a silicon prototype realized using fully differential switched-current circuits in a standard 0.8 μm CMOS technology
  Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on; 06/2001
• Conference Proceeding: Effect of non-linear settling error on the harmonic distortion of fully-differential switched-current bandpass ΣΔ modulators

  J.M. de la Rosa, B. Perez-Verdu, F. Medeiro, R. del Rio, A. Rodriguez-Vazquez
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  ABSTRACT: This paper presents a detailed study of the effect of the non-linear settling on the harmonic distortion of Bandpass ΣΔ Modulators (BP-ΣΔMs) realized using Fully Differential (FD) Switched-current (SI) circuits. Based on the analysis of building blocks, closed-form expressions are derived for the third-order intermodulation distortion of BP-ΣΔMs due to defective settling, on the one hand, and to the non-linearities of the sampling process, on the other. Time-domain simulations and measurements taken from a 0.8 μm CMOS 4th-order BP-ΣΔM silicon prototype validate our approach
  Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on; 06/2001
• Source

  Available from: psu.edu

  Conference Proceeding: High-performance sigma-delta ADC for ADSL applications in 0.35 μm CMOS digital technology

  R. del Rio, J.M. de la Rosa, F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez
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  ABSTRACT: We present a sigma-delta modulator designed for ADSL applications in a 0.35 μm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use an oversampling ratio of only 16 . Special emphasis is placed on technology issues, e.g. poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2 MS/s and 12-bit dynamic range operating at 4 MS/s. The modulator consumes 77 mW from a 3.3 V supply and occupies 1.32 mm²
  Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on; 02/2001
• Source

  Available from: psu.edu

  Conference Proceeding: Top-down design of a xDSL 14-bit 4MS/s ΣΔ modulator in digital CMOS technology

  R. del Rio, J.M. de la Rosa, F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez
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  ABSTRACT: This paper describes the design of a sigma-delta modulator aimed at A/D conversion in xDSL applications, featuring 14-bit@4Msample/s in a 0.35 μm mainstream digital CMOS technology. Architecture selection, modulator sizing and cell sizing tasks where supported by a CAD methodology, allowing one to obtain a power efficient implementation in a short design cycle
  Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings; 02/2001
• Conference Proceeding: A mixed-signal CMOS MODEM ASIC for data transmission on the low-voltage power-line with sensitivity of 283µVrms at 10Kbps

  A. Rodriguez-Vazquez, R. Dominguez-Castro, M. Delgado-Restituto, G. Linan, R. del Rio, J. Ceballos, A. Acosta, J. Ramos
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  ABSTRACT: This paper presents a CMOS 0.8µm mixed-signal half-duplex MODEM ASIC for data transmission on the low-voltage power line. This circuit includes all the analog circuitry needed for input interfacing and modulation/ demodulation (input amplifier, PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, and decision circuitry) plus the logic circuitry needed for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283µVrms¹at 10kbps, and operates correctly in the whole industrial temperature range, from -45 to 80°C, under 5% variations of the 5V supply voltage. This ASIC, which is now in commercial production, has better performance and smaller power consumption than previous commercial low-voltage power-line MODEMs (see Table 1).
  Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26th European; 10/2000
• Source

  Available from: csic.es

  Article: A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion

  J.M. de la Rosa, B. Perez-Verdu, R. del Rio, A. Rodriguez-Vazquez
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  ABSTRACT: This paper presents a CMOS 0.8-μm switched-current (SI) fourth-order bandpass ΣΔ modulator (BP-ΣΔM) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z^-1→-z^-2) to a 1-bit second-order low-pass ΣΔ modulator (LP-ΣΔM). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz
  IEEE Journal of Solid-State Circuits 09/2000; · 3.23 Impact Factor
• Article: Reliable analysis of settling errors in SC integrators: application to ΣΔ modulators

  R. del Rio, F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez
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  ABSTRACT: A study is presented into the transient response of SC integrators considering amplifier finite bandwidth, slew-rate, and parasitic capacitors during, unlike previous models, both the integration and sampling phases. The model is validated by experimental results on a second-order ΣΔ modulator and provides more reliable estimations of the defective settling in high-speed designs than previously reported models
  Electronics Letters 04/2000; · 0.96 Impact Factor
• Conference Proceeding: Reliable analysis of settling errors in SC integrators-application to the design of high-speed ΣΔ modulators

  R. del Rio, F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez
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  ABSTRACT: This paper presents a detailed study on the transient response of SC integrators which takes into account the effects of amplifier finite gain-bandwidth product, slew-rate, and parasitic capacitances. Unlike previous models, both the integration and the sampling phases are considered. Experimental measurements of the settling error power of a 2nd-order ΣΔ modulator are used to validate the model. When compared to previous models, the new one provides more reliable estimations of the defective settling in optimized high-speed ΣΔ modulators. The results in the paper show up to -16 dB difference in the estimation of the in-band error power of a 2-1-1 mb ΣΔM intended for 14 bit@4 M Samples/s
  Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on; 02/2000
• Conference Proceeding: High-order cascade multibit ΣΔ modulators for xDSL applications

  R. Del Rio, F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez
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  ABSTRACT: This paper explores the use of ΣΔ modulators for A/D conversion in xDSL applications. Two high-order multibit architectures, the 2-1-1mb modulator and a novel 2-1-1-1mb cascade (MASH), are proposed to achieve 14 bit dynamic range@4.4 MS/s using low oversampling ratio. They show very low sensitivity to the internal DAC linearity error, with no calibration required. Simulations show this performance can be achieved in presence of circuit imperfections, using submicron digital CMOS processes
  Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on; 02/2000
• Article: A mixed-signal CMOS MODEM ASIC for data transmission on the low-voltage power-line with sensitivity of 283µVrms at 10Kbps

  A Rodriguez-Vazquez, R Dominguez-Castro, M Delgado-Restituto, G Linan, R del Rio, J Ceballos, A Acosta, J Ramos
  [show abstract] [hide abstract]
  ABSTRACT: This paper presents a CMOS 0.8µm mixed-signal half-duplex MODEM ASIC for data transmission on the low-voltage power line. This circuit includes all the analog circuitry needed for input interfacing and modulation/ demodulation (input amplifier, PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, and decision circuitry) plus the logic circuitry needed for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283µVrms¹at 10kbps, and operates correctly in the whole industrial temperature range, from -45 to 80°C, under 5% variations of the 5V supply voltage. This ASIC, which is now in commercial production, has better performance and smaller power consumption than previous commercial low-voltage power-line MODEMs (see Table 1).
  01/2000;
• Article: High-Order Cascade Multi-bit SD Modulators for

  R. del Rio, F. Medeiro, B. Prez-verd, A. Rodrguez-vazquez, Sevilla Centro, Nacional Microelectrnica
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  ABSTRACT: The use of Sigma-Delta (SD) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections.
  08/1999;
• Conference Proceeding: Non-ideal quantization noise shaping in switched-current bandpass ΣΔ modulators

  J.M. de la Rosa, B. Perez-Verdu, R. del Rio, A. Rodriguez-Vazquez
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  ABSTRACT: This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the quantization noise shaping of SI bandpass ΣΔ modulators (BPΣΔMs). Closed form equations are provided for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in order to facilitate the design of this class of modulators. All these results have been validated by nonideal time-domain behavioral simulations
  Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on; 08/1999
• Source

  Available from: csic.es

  Conference Proceeding: Harmonic distortion in fully-differential switched-current sigma-delta modulators

  J.M. de la Rosa, B. Perez-Verdu, F. Medeiro, R. del Rio, A. Rodriguez-Vazquez
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  ABSTRACT: This paper presents a systematic analysis of the harmonic distortion in ΣΔ modulators (ΣΔMs) implemented with fully-differential switched-current (SI) circuits. Closed form expressions are derived for the third-order harmonic distortion in lowpass and bandpass ΣΔMs. For the latter, the third-order intermodulation distortion is also deduced. Time domain behavioral simulations validate our approach
  Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on; 02/1999
• Conference Proceeding: Practical considerations for the design of cascade multi-bithigh-frequency ΣΔ modulators

  F. Medeiro, R. del Rio, B. Perez-Verdu, A. Rodriguez-Vazquez
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  ABSTRACT: Recommendations are given for efficient design of high-frequency ΣΔ modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design with special emphasis on the impact of circuit imperfections. Conclusions are validated by measurements on a 13-bit 2.2 MS/s prototype fabricated in a 0.7 μm CMOS technology
  Electronics, Circuits and Systems, 1998 IEEE International Conference on; 02/1998