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ABSTRACT: Two main aspects of multimedia SoC are addressed in this paper. First, a multiprocessor system employing reconfigurable hardware blocks with coarse and fine grain structures is introduced. It alleviates the tradeoff between computing performance and circuit flexibility for a wide range of applications. Second, a clock generator for synchronous audio and video interfaces is presented. In order to provide high portability and compatibility with the digital design flow it consists of digital standard cells only. Integrated on a 0.25 μm CMOS process, the system occupies 25 mm<sup>2</sup> and operates at 100 MHz. Computation speedup of up to factor 9.7 over stand-alone CPU solutions could be achieved. The clock generator runs at 200 MHz and provides a frequency resolution of 0.06 ppm with an expected output jitter of less than 30 ps; RMS.
Consumer Electronics, 2003. ICCE. 2003 IEEE International Conference on; 07/2003
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ABSTRACT: A digital clock synthesizer consisting of digital standard cells with 0.5ppm frequency resolution for multimedia applications is implemented in a 0.6μm CMOS process. The synthesizer produces an output frequency ranging from 11.1MHz to 12.5MHz with a 100MHz input clock. A DLL-based calibration mechanism tracks PTV variations during operation.
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International; 02/2003
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ABSTRACT: Hardware and software codesign and flexibility requirements often
necessitate embedded application-specific instruction-set processors in
system-on-chip designs. Spaceman, a reusable stack-processor virtual
component, offers a customer-configurable instruction set;
parameterizable bus widths, stack depths, and stack access ranges; and
selectable bus interfaces
IEEE Micro 04/2001; · 1.78 Impact Factor
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ABSTRACT: We have implemented a SONET/SDH compatible 155 Mbit/s input block
using a new paradigm called programmable intellectual property. The
module can be reconfigured by downloading new software versions into the
IP embedded processor. This concept offers maximum flexibility for both
hard- and soft-IP modules
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000; 02/2000
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ABSTRACT: A novel architecture for an ultra compact
Add-Drop/Terminal-Multiplexer for Synchronous Digital Hierarchy (SDH)
telecommunication networks is reported. This new architecture allows one
to integrate all digital functions into one ASIC (except the System
Control Unit). The minimally configured complete system occupies only
one single card of size 235 mm×265 mm. If protection is required
two identical cards are used. The key features to obtain a single chip
solution are a novel protection scheme, a new data path which needs just
one single buffer with integrated switch matrix functionality, and an
embedded processor which substitutes various large hardware blocks
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International; 02/1999
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ABSTRACT: Scalability and customization properties of IP modules demand for new approaches in functional verification. We present a novel simulation-based solution for an Application-specific Instruction-set Processor (ASIP). Existing assembler code preselected by IP-configurable constraints forms the verification data base (reference stimuli). A behavioral “golden model” of the IP is used to derive expected responses suitable for any possible configuration of the final ASIP (RTL) implementation. Cycle-based verification is performed by stimulating the RTL model with the assembled reference stimuli and by comparing the outputs (actual responses) against the expected responses. Primary input stimulation is accomplished by reading back interface data prior written to a memory (model) under control of the reference stimuli. The synchronization of the configaration-dependent actual responses to the non-cycle-related expected responses is achieved by a mechanism based on “interface-specific activity scheduling”, which further more reduces the number of vectors efficiently, resulting in a significant simulation speed-up
Test Conference, 1999. Proceedings. International; 02/1999
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ABSTRACT: Customizable microprocessors pose numerous design problems that
arise from application-specific needs for data operations, word widths,
storage capacities, and interfaces. We present a stack processor that
features a customizable instruction set, extensive parametrization, and
a synthesis model with separate core and interface modules. Verification
uses a reference model automatically derived from a generic model and
the current parameter settings
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International; 02/1999
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ABSTRACT: In this paper we present an application-specific microprocessor
core with a stack architecture optimized for use in broadband
telecommunication ASICs. The microprocessor was integrated in an
application on the same die as the complete data path of an SDH add-drop
multiplexer (ADM). It handles over 1 million interrupts per second from
29 asynchronous sources. Due to this high interrupt rate extremely
efficient context switching is required: only two extra cycles per
interrupt call. The top four stack elements are directly accessable as
registers and ALU instructions are computed in parallel with push or pop
commands. An independent ALU for address processing enables compact and
very efficient code generation. A prototype ASIC has been implemented in
0.8 μm CMOS technology
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998; 06/1998
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ABSTRACT: During the development of a STM-1 add-drop multiplexer (ADM-1) we
gained new experiences for efficient hardware/software co-design of such
complex telecommunication systems. The chosen partitioning between
hardware and software can be seen as typical for broadband
telecommunication applications. The payload is processed in hardware
while the management overhead is treated in software. To obtain an
efficient hardware/software interface and to get optimal real-time task
scheduling all software processes are interrupt driven. We developed a
processor core with a stack architecture, which is optimized to handle
that many interrupts. It yields a very area-efficient implementation.
Besides many other benefits this hardware/software co-design solution
uses approximately 52 KGE compared to the 81 kGE of a pure hardware
implementation, and enhances its flexibility
Global Telecommunications Conference, 1998. GLOBECOM 98. The Bridge to Global Integration. IEEE; 02/1998
