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ABSTRACT: The gate oxide is the most fragile element of metal-oxide-semiconductor (MOS) transistor. Metal contamination is fatal to gate oxide integrity because metallic contamination in the gate oxide leads to high leak current and even gate oxide breakdown. In this paper, a case of gate oxide integrity failure was investigated. The fact that the emission spot locates in the bulk area instead of poly edge excludes the possibility of failure cause of poly/spacer etch, gate oxide thinning at the edge or gate oxide thinning at STI corner issue. Molybdenum (Mo) contamination was detected in the gate oxide of NMOS using magnetic sector secondary ion mass spectrometry because of its excellent sensitivity. The results showed that Mo contamination is introduced in the process of germanium pre-amorphization implantation mainly in the form of (<sup>98</sup>Mo<sup>12</sup>C<sup>19</sup>F<sub>2</sub>)<sup>++</sup>, which has the same nominal mass to charge ratio as <sup>74</sup>Ge<sup>+</sup>. The different properties of poly-Si resulted in that NMOS but not PMOS was affected by the Mo contamination. Unlike iron (Fe) contamination, Mo contamination is rarely reported in the GOI failure. On the basis of that, suggestions have been proposed to greatly suppress the Mo contamination.
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the; 08/2008
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ABSTRACT: Interfacial characterization of ultra low-k film with the layer underneath is very important for reliable manufacturing of ultra low-k film. In this study, we proposed a new application of TOF-SIMS to predict the interfacial behavior of the ultra low-k with the layer underneath. Strong correlation between carbon intensity at the bottom interface with the adhesion energy of the ultra low-k with the layer underneath is observed. We also observed a linear correlation between the quantified carbon peak intensity and the adhesion energy.
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the; 08/2008
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ABSTRACT: Mobile ions may cause critical failures in integrated circuits. For silicon-on-insulator (SOI) wafers, the mobile ions affect not only the reliability of back end of the line but also the performance of the transistors. This paper presents a case study of potassium (K) contamination in the SOI wafer using dynamic secondary ion mass spectrometry. The results showed that the presence of K in chemical and mechanical polish slurry contaminated the porous interlayer dielectrics (ILD), penetrating below the surface due to their porous structure. The K contamination has been greatly reduced by capping the porous ILD with a high-density-oxide layer.
IEEE Transactions on Device and Materials Reliability 07/2007; 7(2):369-372. · 1.54 Impact Factor
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ABSTRACT: In this paper, a case study of BIST failure in SOI wafer fabrication was presented. With optimized charge neutralization using a well-controlled normal incident electron beam, a reliable depth distribution of K in the ILD was obtained which is helpful to understand the source of K contamination. From the SIMS and EDX results, the root cause was concluded to be K contamination introduced by the CMP slurry. The yield has been improved greatly by depositing a layer of high density oxide on the top of ILD to block the K contamination
Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the; 08/2006
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ABSTRACT: A case of the application of passive voltage contrast (PVC) and
focused ion beam (FIB) to failure analysis of metal interconnection or
via defects in wafer fabrication was studied. We have proposed a simple,
efficient and cost-saving identification method of locating the 1st,
2nd, 3rd and higher defective vias in the via chain through FIB-induced
PVC and its precise cross-sectioning. Such a technique proves useful as
it enables us to understand whether all the defective vias in the via
chain exhibit the same failure phenomenon or display any particular
failure pattern which will help the failure analysis or process
engineers to determine the failure mechanism
Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the; 02/2001
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ABSTRACT: The poly residue problem in wafer fabrication was investigated in
this paper. Surface and cross sectional SEM (scanning electron
microscopy) was used to identify the root cause. After poly etching,
particle contamination was found at the N-well and field oxide overlap
region. Some wafers were scrapped due to this issue. To identify the
root cause and solution, some affected wafers were subjected to surface
and cross sectional SEM. Surface SEM inspection found the particles at
the edge of field oxide. Cross sectional SEM and EDX confirmed that it
was poly residue. The residue was due to the high topography at the edge
of the field oxide, thus causing higher poly thickness. The difference
in height resulted in the vertical thickness of the slope of ONO and
poly layers to be thicker than that of the planar layer. During the poly
etch process, which was anisotropic, the planar poly could be etched
away completely but the poly at the slope might not be etched away as it
was thicker than the planar layer. Hence some poly residue was left
behind. After investigation, the solutions used are to optimize the poly
etching recipe by removing He clamp flow at the break through step, and
to increase the isotropic etch and etching time from 80 s to 100 s. The
poly residue is then eliminated after implementing the new etch recipe
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on; 02/2000
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ABSTRACT: In this paper, silicon nodules due to Si precipitation were investigated in wafer fabrication. Line inspection found particle contamination on bondpads and large metal 1 lines of some wafers. Cross sectional SEM results showed that some nodules were found in the metal 1 layer. EDX analysis confirmed that they were Si nodules as a high Si peak was detected on the nodules. These nodules had resulted in open failure in some metal lines. Based on the failure analysis results, we concluded that the silicon nodules were due to silicon precipitation. The preventive actions taken were to check the target if the Si value in Al exceeds the normal value, to control the parameter strictly during metal deposition and to reduce the thermal cycles after metal deposition
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on; 02/2000
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ABSTRACT: In this paper, a case of bondpad peeling was investigated. EDX (energy-dispersive X-ray microanalysis) and AES (Auger electron spectroscopy) techniques were used to identify the possible root cause. Based on EDX and AES results, it is concluded that the bondpad peeling problem was due to significant carbon contamination on the peeled area of the bondpad, which might contribute to the bondpad peeling problem. EDX and AES results also confirmed the peeling occurred between the barrier metal and BPSG layers. The high C contamination had resulted in poor adhesion between the barrier metal and BPSG layers and resulted in the peeling problem. The high C contamination on the BPSG layer was introduced during the wafer fab process. It may be due to incomplete contact process resist strip or insufficient pre-clean before barrier metal deposition. In this paper, we also discuss the difference between EDX and AES analysis techniques and use the contamination diagram introduced by us
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on; 02/2000
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ABSTRACT: Metal 1 sidewall polymer contamination was investigated in wafer fabrication. SEM and EDX techniques were used to identify the root cause. After metal 1 etching, particle contamination was found on metal 1 lines. Cross sectional SEM results showed the contamination was at the side of the metal lines. EDX results showed that C and Cl elements were detected. Failure analysis results indicated that the contamination was most likely sidewall polymer introduced during metal etching. Further fab investigation found that the sidewall polymer contamination was due to gas flow drifting from set point during metal etches. The solution is that the mass flow control is calibrated using two set points (at 30 and 60 sccm). This new calibration procedure was able to detect the MFC linearity problem. After implementing the two point calibration method, the sidewall polymer contamination was eliminated
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on; 02/2000
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ABSTRACT: Some lots of wafers were reported with low yield due to ANADC pattern functional failure. SEM, EDX and 155 Wright etch techniques were used to identify the root causes. Cross sectional results found the nodules on substrate at the contact area. EDX analysis confirmed them to be silicon nodules. After 155 Wright etch (100) square silicon crystalline hillocks were found on the substrate at the contact area. It is concluded that silicon nodules on the substrate at the contact area had resulted in an open circuit and low yield. These silicon nodules were due to Si precipitation on the substrate of the contacts
Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on; 02/1998
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ABSTRACT: A study was conducted on EKC265 cleaning bath life. The Auger
analysis technique was used to evaluate the contamination levels of
fluorine and carbon on the bond pad after the EKC265 process. The
results showed that it is necessary and effective to perform EKC265
cleaning for L95 lots. The contamination levels of C and F on the
surface (0 Å) of bond pads were about 20 at% and 7.5 at% at the
bath life of 40 lots used currently. However, they were 0 at.% at a
depth of 50 Å. The results also show that it is possible to extend
EKC265 bath life from 40 lots (6 inch) to 50 lots (6 inch) for cost
reduction purposes
Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on; 02/1998
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ABSTRACT: Silicon crystalline defects in production silicon wafers affect the yield. In this paper, the 155 Wright etch was used to identify the root causes of silicon crystalline defects. A few low yield cases are studied and the different types of crystalline defects and their possible root causes and preventative measures taken are discussed
Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on; 02/1998
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ABSTRACT: Aluminum bond pads on semiconductor chips play an important role
in IC device reliability and yield. Contaminated Al bond pads can cause
poor intermetallic growths, thus failed or unreliable connections from
the chip to the outside world. Utilizing FIB, SEM and EDX techniques,
the contamination analysis may be carried out to reveal and identify
defects underneath Al layer. In this study, three cases of Al bond pads
with underneath contamination were investigated using this analysis
approach. Based on the FIB/SEM/EDX analysis results, contamination root
causes are discussed and suggested
Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on; 08/1997
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ABSTRACT: A case of multiple failures at the end of line (EOL) electrical test (E-test) was encountered in wafer fabrication. In this paper, we will present a significant study of multiple E-test failure case, using CAMECA IMS Wf instrument. The results show that the failure is relate to the quality of incoming starting materials.
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the;
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ABSTRACT: The stopping power of photo-resist is an important parameter to define the photoresist thickness. In this paper, we have developed a novel method to the stopping power of the photo-resist. This method is to directly determine the implantation profile in the photo-resist using secondary ion mass spectrometry (SIMS) due to its excellent sensitivity and high depth resolution. We have obtained the depth distribution of dopants, such as boron, arsenic, phosphorous and indium, in the photo-resist using CAMECA Wf SIMS machine. The results obtained with the novel method are straightforward and unambiguous, compared to the conventional method. The safe photo-resist thickness has been optimized based on the SIMS results.
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on;
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ABSTRACT: The gate oxide is the most fragile element of metal-oxide-semiconductor (MOS) transistor. Metallic contamination in the gate oxide leads to high leak current and even gate oxide breakdown. In this paper, we have investigated a failure case of NMOS gate oxide breakdown using secondary ion mass spectrometry (SIMS) because of its excellent sensitivity. The SIMS depth profiles at the test pad in the scribe line showed that the gate oxide breakdown was caused by tungsten (W) contamination. Further study indicated that W contaminated wafers during n-poly implantation by the re-deposition from the supporting disk of implanter. Based on the SIMS results, measures have been suggested to reduce the W contamination.
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on;
