R. Bolam

IBM, Armonk, New York, United States

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Publications (13)3.28 Total impact

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    ABSTRACT: A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments employing both AC and DC stress/relax BTI measurements are undertaken to characterize FET's threshold voltage instability response to a dynamic (inverter type) operation. Results from the AC stress experiments demonstrate that VT instability is frequency independent, an observation that suggests that VT degradation under AC stress can be equivalently measured through the simpler DC stress/relax sequence. An AC BTI model is developed that accurately captures the critical BTI relaxation effect through the DC stress/relax predictions on duty cycle dependence. A Ring Oscillator (RO) circuit is used as a model verification vehicle. Excellent agreement is demonstrated between the frequency degradation measurements obtained with a newly developed Ultra-Fast On-The-Fly (OTF) measurement technique optimized for BTI and the AC BTI model based RO simulations.
    01/2011; DOI:10.1109/IRPS.2011.5784559
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    ABSTRACT: Based on fundamental understanding of oxide breakdown (BD) physics established for thin oxides, we demonstrate that product circuit malfunction such as SRAM V<sub>min</sub> failure due to intrinsic TDDB can be accurately predicted. This prediction is based on a viable methodology using power-law voltage acceleration and progressive BD.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (V<sub>dd</sub>=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum<sub>2</sub>
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: The effect of negative bias stress on p-FETs is compared for oxide vs. oxynitride gate dielectric, and for (110) vs. (100) surface orientation. Nitrogen causes increased interface state generation near the conduction band edge and reduced defect generation at mid-gap. For oxynitride grown on (110) surface only slight difference is seen compared to (100). The hole trapping contribution to the Vt shift is greater at room temperature compared to 125 °C.
    Microelectronic Engineering 06/2005; 80:126-129. DOI:10.1016/j.mee.2005.04.027 · 1.34 Impact Factor
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    ABSTRACT: In these experiments, we explored various methods of nitridation of thermal oxide. Rapid thermal oxidation (RTO), rapid thermal oxidation with nitric oxide (RTNO), remote plasma nitridation (RPN), and decoupled plasma nitridation (DPN) processes were performed, and the result on 1.4, 2.2, and 5.2 nm oxides was measured. It is shown that the initial threshold voltage and the shift during negative bias temperature instability (NBTI) stress are proportional to the nitrogen in the oxide. Not surprisingly the threshold voltage is dependent on the interfacial nitrogen, but it was also found that the NBTI shift depends on the total nitrogen incorporated throughout the bulk of the insulator. The thinnest oxide showed boron penetration for the unnitrided split, but also very low NBTI shift. Furthermore, wafers from each of the aforementioned nitridation variants were processed with and without deuterium passivation. Although the NFET hot–carrier response is substantially improved, no significant advantage in NBTI shift is observed.
    Microelectronics Reliability 01/2005; 45(1-45):47-56. DOI:10.1016/j.microrel.2004.02.016 · 1.43 Impact Factor
  • E. Wu · W. Lai · M. Khare · J. Sune · L.-K. Han · J. McKenna · R. Bolam · D. Harmon · A. Strong
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    ABSTRACT: The polarity-dependent oxide breakdown of NFET devices has been carefully studied for ultra-thin gate oxides. The measurement of charge-to-breakdown, Q<sub>BD</sub>, is found to be consistently lower for the gate injection mode than that of the substrate injection mode for the range of oxide thickness investigated here. On the other hand, the time-to-breakdown, T<sub>BD</sub>, of the gate and substrate injection modes, shows a crossover behavior as oxide thickness is reduced. The possible mechanisms are discussed to explain the degradation in QBD under the gate injection mode. Because of important implications for SOI technology applications, we have conducted a systematic reliability evaluation of NFET devices under the gate injection mode. Thickness, voltage, and temperature dependences of T<sub>BD</sub>(Q<sub>BD</sub>) as well as for the Weibull slopes have been extensively characterized. The results of these studies indicate that the trend in these dependencies is very similar to what was previously found for the substrate injection mode, such as the power-law T<sub>BD</sub> voltage dependence and temperature-independent voltage acceleration.
    Reliability Physics Symposium Proceedings, 2002. 40th Annual; 02/2002
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    ABSTRACT: Understanding the reliability implications for silicon-on-insulator (SOI) is crucial for its use in ULSI technology. The fabrication process of SOI material and the device operation, due to the buried oxide (BOX) layer, could present additional concerns for meeting reliability requirements. In this paper, we discuss the reliability issues with silicon-on-insulator (SOI) technology. We focus on partially depleted (PD) SOI CMOS technology using SIMOX and bonded substrate material. We compare the reliability mechanisms, namely channel hot electron (CHE), gate oxide time dependent dielectric breakdown (TDDB), bias temperature stress (BTS) and plasma-induced charging damage, to bulk CMOS. In addition, results from high performance microprocessors subjected to burn-in stress are presented. Finally, we discuss the circuitry implications for electrostatic discharge (ESD)
    Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
  • Terence B. Hook · Jay S. Burnham · Ronald J. Bolam
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    ABSTRACT: Device characteristics and reliability in a 3.3-V logic CMOS technology with various gate oxidation and nitridation processes are described. The technology was designed to extend 3.3-V devices to the ultimate dielectric reliability limit while maintaining strict manufacturing cost control. A nitrided gate oxide provided the means to maintain hot-electron reliability at the level of the previous iteration, but at higher performance and lower processing cost. Conventional furnace processes in nitrous and nitric oxide, high-pressure oxidation in oxygen and nitrous oxide, and rapid-thermal processes using nitrous and nitric oxide were investigated. We found that the concomitant variations in fixed charge and thermal budget have a significant influence on both n-FET and p-FET device parameters such as threshold voltage, carrier mobility, and inverse short-channel effect (ISCE). Reliability effects, such as charge to breakdown (QBD), hot-electron degradation, and negative-bias temperature instability (NBTI) were examined and correlated with the nitrogen profile in the gate dielectric. Secondary ion mass spectroscopy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters.
    Ibm Journal of Research and Development 05/1999; 43:393-406. DOI:10.1147/rd.433.0393 · 0.50 Impact Factor
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    ABSTRACT: A 0.22 μm CMOS on SOI technology, using a nonfully depleted device, is developed. This technology uses the same gate lithography and metallization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furthermore, it offers the complete device and circuit elements used in bulk CMOS (low V<sub>T</sub> device, ESD diode, and decoupling capacitance). This technology was applied to a 64 b RISC processor
    VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
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    ABSTRACT: Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. In this paper, the challenges of mainstreaming the SOI technology in device, material, technology and circuit terms are described
    SOI Conference, 1999. Proceedings. 1999 IEEE International; 02/1999
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    ABSTRACT: The scalability of SOI CMOS technology into the low voltage high performance regime and its comparison with bulk CMOS technology is presented. Based on ring oscillator performance, the 0.13 μm SOI CMOS technology can achieve more than 25% faster speed and/or 50% less active power compared to a similar bulk technology
    Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International; 01/1999
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    ABSTRACT: In this paper we demonstrate the fastest CMOS circuits reported to date. At room temperature the unloaded CMOS inverter delay as low as 7.85 psec is measured. This number drops to 5.5 psec at liquid nitrogen temperature. The devices used in the study are built on SOI, with excellent short-channel characteristics down to 0.06 μm for the NFETs and 0.08 μm for the PFETs. Although devices with high threshold voltages are used, record delays are achieved at relatively low supply voltages. At 1.8 V, the inverter delay is 8.3 psec and 5.9 psec at T=300 K and T=80 K, respectively. The corresponding delays at 1.2 V are 11.4 psec and 8.2 psec. Through proper device optimization, we demonstrate that undesired SOI floating-body effects are minimized as well. These results demonstrate that there is significant room for continued performance enhancement in scaled CMOS
    Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International; 01/1998
  • A. Strong · E. Wu · R. Bolam
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    ABSTRACT: Voltage life-stress results have been compared with voltage step stress results. The figure of merit chosen for this comparison was TDDB. Two different oxides were used, one having a thickness of 13.5 nm and the other having a thickness of 8.2 nm
    Integrated Reliability Workshop, 1995. Final Report., International; 11/1995