[show abstract][hide abstract] ABSTRACT: This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (A<sub>VT</sub>) improvement (A<sub>VT</sub>~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um<sup>2</sup> SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
[show abstract][hide abstract] ABSTRACT: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum<sup>2</sup>. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V V<sub>dd</sub> with a low cost process. With this high performance transistor, V<sub>dd</sub> can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L<sub>gate</sub> = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.
[show abstract][hide abstract] ABSTRACT: To achieve a lower gate leakage in high speed devices at the same equivalent oxide thickness, a major thrust is to replace the SiO<sub>2</sub> with a thicker dielectric that has a higher dielectric constant. Recently, there has been much interest in hafnium dioxide as a potential high-k gate dielectric as presented in E. P Gusev et a. (2001), B. Barlage et al. (2001), G. Wilk et al. (2001), C. Hobbs et al. (2001), W. Zhu et al. (2001), W. Qi et al. (2000) and B. Lee et al. (1999) due to its high permittivity. However, the polycrystalline microstructure may be undesirable. In order to increase the crystallization temperature, SiO<sub>2</sub> or Al<sub>2</sub>O<sub>3</sub> are added to HfO<sub>2</sub> to form Hf silicates atid Hf aluminates. A systematic study to compare the device characteristics of these three major candidates is needed. In this work, we have compared them in terms of the key challenges of high-K devices such as Gm degradation, Vt instability, and reliability, in devices fabricated with a conventional CMOS process technology according to A. Perera et al. (2000).
[show abstract][hide abstract] ABSTRACT: We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO<sub>2</sub>, Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub> for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.
[show abstract][hide abstract] ABSTRACT: Device instability is one of the most challenging issues to implement high-k gate dielectrics. Incorporation of deuterium during the ALD (atomic layer deposition) process effectively improves the interface quality that enhances high-k device stability and reliability. Compared to H<sub>2</sub>O processed HfO<sub>2</sub> devices, devices with D<sub>2</sub>O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125°C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD high-k gate dielectric processing is the final choice.
[show abstract][hide abstract] ABSTRACT: As traditional poly-silicon gated MOSFET devices scale, the additional series capacitance due to poly-silicon depletion becomes an increasingly large fraction of the total gate capacitance, excessive boron penetration causes threshold voltage shifts, and the gate resistance is elevated. To solve these problems and continue aggressive device scaling we are studying metal electrodes with suitable work-functions and sufficient physical and electrical stability. Our studies of metal gates on HfO2 indicate that excessive inter-diffusion, inadequate phase stability, and interfacial reactions are mechanisms of failure at source drain activation temperatures that must be considered during the electrode selection process. Understanding the physical properties of the metal gate – HfO2 interface is critical to understanding the electrical behavior of MOS devices. Of particular interest is Fermi level pinning, a phenomenon that occurs at metal – dielectric interfaces which causes undesirable shifts in the effective metal work function. The magnitude of Fermi level pinning on HfO2 electrodes is studied with Pt and LaB6 electrodes. In addition, the intrinsic and extrinsic contributions to Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the work function of platinum-HfO2-silicon capacitors. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone. Interface chemistry and defects influence the effective metal work function.
[show abstract][hide abstract] ABSTRACT: We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub>, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.
[show abstract][hide abstract] ABSTRACT: Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO2 at conventional temperatures (near 620 °C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO2 films using metal gates or silicon gates with low temperature deposition. However, depositing conventional CVD poly-Si gates directly onto Al2O3-capped, hafnium–silicate-capped, or physical vapor deposition (PVD) silicon-capped HfO2 resulted in the absence of large inhomogeneous poly-Si grains and well behaved capacitors with leakage reduction greater than 103 times compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO2 are attributed to a partial reduction of the HfO2 by the poly-Si deposition ambient. In the first case (1) the partial reduction occurs locally on the HfO2 surface, forming Hf–Six bond(s) which act as nucleation points for crystalline silicon growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.
[show abstract][hide abstract] ABSTRACT: We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
[show abstract][hide abstract] ABSTRACT: We report for the first time electrical characterization of HfO<sub>2</sub> p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO<sub>2</sub> and SiO<sub>2</sub> n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10 nA/μm leakage, 0.345 mA/μm drive current was obtained from PVD TiN/HfO<sub>2</sub> p-MOSFETs. HfO<sub>2</sub> n-MOSFETs with metal gates show about 10<sup>4</sup> times reduction in gate leakage compared to poly/SiO<sub>2</sub> devices.
[show abstract][hide abstract] ABSTRACT: The electrical performance of column IVB metal oxide thin films
deposited from their respective anhydrous metal nitrate precursors show
significant differences. Titanium dioxide has a high permittivity, but
shows a large positive fixed charge and low inversion layer mobility.
The amorphous interfacial layer is compositionally graded and contains a
high concentration of Si-Ti bonds. In contrast, ZrO<sub>2</sub> and HfO
<sub>2</sub> form well defined oxynitride interfacial layers and a good
interface with silicon with much less fixed charge. The electron
inversion layer mobility for an HfO<sub>2</sub>/SiO<sub>x</sub>N<sub>y
</sub>/Si stack appears comparable to that of a conventional SiO<sub>2
IEEE Transactions on Electron Devices 11/2001; · 2.06 Impact Factor
[show abstract][hide abstract] ABSTRACT: We report here for the first time the formation of an amorphous
oxide layer between the polysilicon gate and hafnium oxide (HfO<sub>2
</sub>) gate dielectric due to a lateral oxidation mechanism at the gate
edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm
MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv
of 25 Å with a leakage current 1000× lower than SiO<sub>2
</sub> was obtained for a 30 Å HfO<sub>2</sub>/12 Å
interfacial oxide stack. In this paper, we present results on the
physical and electrical characterization
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
[show abstract][hide abstract] ABSTRACT: MOSFETs with a zirconium dioxide (ZrO<sub>2</sub>) gate dielectric
and poly-silicon gate were fabricated using a low temperature CMOS
process. Well-behaved transistor characteristics were obtained for
devices with sizes of 14 μm×1.4 μm or smaller. Devices 14
μm×14 μm or larger were found to be nonfunctional due to the
formation of Zr-silicide at the polySi-gate/Zr0<sub>2</sub> interface.
In this paper, we present results on the electrical and physical
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on; 02/2001
[show abstract][hide abstract] ABSTRACT: The increase in gate leakage current and boron penetration are major problems for scaled gate dielectrics in advanced device technology. We have demonstrated, for the first time, reduction in gate leakage current and strong resistance to boron penetration when jet vapor deposition (JVD) nitride is used as a gate dielectric in an advanced CMOS process. JVD nitride provides a robust interface in addition to well behaved bulk properties, MOSFET characteristics and ring oscillator performance. Process optimization is discussed. Manufacturing issues remain to be addressed.
[show abstract][hide abstract] ABSTRACT: We report here for the first time the integration of sub-quarter
micron CMOSFETs on bulk silicon using an oxidized metal gate dielectric.
A polysilicon capped physical vapor deposited (PVD) titanium nitride
(TiN) was used as the gate electrode. Well behaved MOSFET
characteristics were obtained. In this paper, we present results on the
physical and electrical characterization of titanium dioxide (TiO<sub>2
</sub>) produced by oxidizing a thin PVD Ti film