Wen Chao Shen

National Tsing Hua University, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (10)15.33 Total impact

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    ABSTRACT: A high density high-k gate dielectric breakdown OTP cell with a self-aligned twin-gate isolation in pure 28nm HKMG process is demonstrated. With a merged spacer isolation formed by two tiny metal gates, the OTP cells can be well isolated with an ultra small cell size of 0.0441μm2 in pure 28nm CMOS logic process. The Twin-Gate OTP memory adopts low voltage high-k dielectric breakdown mechanism to obtain 104 times of On/Off ratio by a low program voltage of 4V in 20μs. A tiny and excellent Twin-Gate isolation with wide program and temperature margins has been successfully achieved in this OTP cell. Superior disturbs immunity and data retention further support the new logic OTP cell to be a promising solution in advanced logic NVM applications.
    2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA); 04/2014
  • Japanese Journal of Applied Physics 03/2014; 53(4S):04ED08. · 1.06 Impact Factor
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    ABSTRACT: A new 2-transistor logic ReRAM cell with 28nm high-k metal gate (HKMG) and fully CMOS logic compatible process is reported. The new 28nm logic compatible RRAM cell consists of two logic standard high-k metal gate CMOS transistors by an optimized composite resistive gate dielectric film TiN/HfO2/TiN as a storage node in the cell and as a gate dielectric in the select transistor. Using the cell gate as a source line for RRAM set/reset operation, the resistive memory states can be read and sensed by the selection of the select transistor and its bitline. As a result, the new 2-transistor CMOS logic ReRAM cell is very area-saving, cost effective, and fully compatible with advanced high-k metal gate CMOS logic technology platform. By adapting the highly manufacturable high-K gate dielectric in embedded ReRAM cell, the cell does not need any additional deposition of the resistive film or extra process steps, as a result, it will be easily scaled down and following by the CMOS technology evolution, besides it can be simply dropped on a logic IP or circuits for the need of NVM array or discrete storages in advanced SOC logic-NVM applications.
    IEEE Electron Device Letters 10/2013; 34(10):1253-1255. · 3.02 Impact Factor
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    ABSTRACT: This letter presents a novel high density differential split gate flash memory with self-boosting function realized by 0.18- μm embedded memory technology from Taiwan Semiconductor Manufacturing Company. The cell has a pair of symmetric floating gates to perform differential read for storage electrons in the dual gate. Besides, a simple and nondecoding self-boosting operation is built in to automatically boost threshold levels of the symmetric cells to prevent a long-term charge loss or data degradation problem. Since the cell process and tip erase structure are totally inherited from the proven split-gate flash technology, the highly efficient program and erase performances are remained in the new cell. This implemented self-boosting operation provides a promising solution for reliable embedded memory for advanced CMOS technology.
    IEEE Electron Device Letters 09/2013; 34(9):1127-1129. · 3.02 Impact Factor
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    ABSTRACT: A new type of true random number generator, based on the random telegraph noise of a contact-resistive random access memory device, is proposed in this letter. The random-number generator consists of only a simple bias circuit plus a comparator, leading to small circuit area and low power consumption. By realizing this generator by the 65-nm complementary metal-oxide-semiconductor logic process, the occupied area can be as low as 45 μm2, demonstrating substantial saving in the circuit area.
    IEEE Electron Device Letters 08/2012; 33(8):1108-1110. · 3.02 Impact Factor
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    ABSTRACT: The intense development and study of resistive random access memory (RRAM) devices has opened a new era in semiconductor memory manufacturing. Resistive switching and carrier conduction inside RRAM films have become critical issues in recent years. Electron trapping/detrapping behavior is observed and investigated in the proposed contact resistive random access memory (CR-RAM) cell. Through the fitting of the space charge limiting current (SCLC) model, and analysis in terms of the random telegraph noise (RTN) model, the temperature-dependence of resistance levels and the high-temperature data retention behavior of the contact RRAM film are successfully and completely explained. Detail analyses of the electron capture and emission from the traps by forward and reverse read measurements provide further verifications for hopping conduction mechanism and current fluctuation discrepancies.
    Journal of Applied Physics 04/2012; 111(7):73701-737015. · 2.19 Impact Factor
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    ABSTRACT: A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528µm2 by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell uses the source side injection (SSI) to obtain 100 times of on/off window by a low program voltage of 3.5V within 1msec. A good reliability in retention and disturb is exhibited due to the inherently decoupling of storage node and transistor gate oxide in this cell, even when gate oxide is thinner than 16Å with 32nm gate length only.
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    ABSTRACT: A new high density Contact RRAM (CRRAM) cell realized in pure high-k metal gate 28nm CMOS logic process with a very small 35nm×35nm resistive contact hole has been fabricated without extra masking or process step. This study reports the first time of a manufacturable tiny resistive node of RRAM cell on a 28nm CMOS logic platform and fully compatible with high-k metal gate processes. The 28nm Contact RRAM cell exhibits a stable operation window with a very small cell size of 0.03μm2. Due to the scale down and uniform manufacturing process, the cell reliably operates in a low set voltage of 3V and an acceptable reset current of 60μA/cell with short set and reset time of 500ns and 100us. Excellent endurance of more than 1M cycles and stable data retention at high temperature further support the 28nm Contact RRAM will be a promising SOC memory i n the future.
    Electron Devices Meeting (IEDM), 2012 IEEE International; 01/2012
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    ABSTRACT: In this letter, we proposed a novel operation of a share contact resistive random access memory (CRRAM) structure to realize a nonvolatile latch (NV latch) with a single transistor. With a share CRRAM structure and sequential input operations, the NV latch as well as and/ or functions have been successfully demonstrated. The new mixing approach of combining memory and logic in a single unit projects the possibility of new applications for VLSI circuits.
    IEEE Electron Device Letters 01/2011; 32(12):1650-1652. · 3.02 Impact Factor
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    ABSTRACT: Single electron trapping/de-trapping behavior is firstly observed and investigated in the contact resistive random access memory cell. By analyzing the random telegraph noise, the temperature-dependency of resistance levels and the high-temperature data retention behavior of the contact RRAM film are successfully explained. Detail analyses on the capture and emission of electrons in this contact RRAM cell provide further verifications for the proposed trap-induced resistive switching model.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2010;