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Publications (3)0 Total impact

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    ABSTRACT: In complex System on Chips (SoCs), system level platforms are built around a set of IPs including processor cores, memories and dedicated hardware (FPGA, ASIC). The better for modeling is using a single system level language during implementation. However, as IPs are in different languages, there is a need to several adaptations and conversion processes, hence making the platforms un-optimized.In this paper we fit the optimization problems by enhancing performances of SystemC SoC platforms according to a treble: productivity, simulation speed and improved verification. We enabled the two first using ST Microelectronics mature techniques and the third with a novel assertion-based verification that we proposed in this paper. As experimentation we used realistic IPs from ST Microelectronics and ARM in order to build the SoC platforms. Among these IPs, some are modeled in VHDL, some other are in Verilog and the rest are in SystemC.
    Microprocessors and Microsystems. 01/2007;
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    ABSTRACT: The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the ST Microelectronics system flow: transaction level modeling (TLM). A new assertion-based verification approach is proposed. It consists of a runtime simulation of the system-on-chip (SoC) under verification with PSL checkers. In this approach, the PSL checkers that represent the system specification are converted into C++ and therefore into a SystemC-TLM modules, which refer to us as TLM checkers. However, when integrating TLM checkers with SystemC models of SoC, the traditional clock-based synchronization at register transfer level and lower could not be applied. In fact, at the TLM abstraction level, the modeling rules forbid the use of a hardware clock. A new synchronization policy should be then proposed, hence the aim of this paper
    Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on; 10/2006
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    ABSTRACT: SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage
    Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on; 10/2006