M. Yabuuchi,
K. Nii,
Y. Tsukamoto,
S. Ohbayashi,
S. Imaoka,
H. Makino,
Y. Yamagami, S. lshikura,
T. Terano,
T. Oashi,
K. Hashimoto,
A. Sebe,
G. Okazaki,
K. Satomi,
H. Akamatsu,
H. Shinohara
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ABSTRACT: A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided V<sub>DD</sub> line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum<sup>2</sup> and 0.327mum<sup>2</sup> are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
