M. Harwood,
N. Warke,
R. Simpson, T. Leslie,
A. Amerasekera,
S. Batty,
D. Colman,
E. Carr,
V. Gopinathan,
S. Hubbins, [......],
S. Lytollis,
A. Pickering,
M. Saxton,
D. Sebastio,
G. Swanson,
A. Szczepanek,
T. Ward,
J. Williams,
R. Williams,
T. Willwerth
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ABSTRACT: A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10<sup>-15</sup> is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm<sup>2</sup> per TX/RX pair
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
