[Show abstract][Hide abstract] ABSTRACT: The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change–based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change–based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change–based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates.
Proceedings of the National Academy of Sciences 09/2014; · 9.81 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35f J read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.
[Show abstract][Hide abstract] ABSTRACT: Learning scheme is the key to the utilization of spike-based computation and the emulation of neural/synaptic behaviors toward realization of cognition. The biological observations reveal an integrated spike time- and spike rate-dependent plasticity as a function of presynaptic firing frequency. However, this integrated rate-temporal learning scheme has not been realized on any nano devices. In this paper, such scheme is successfully demonstrated on a memristor. Great robustness against the spiking rate fluctuation is achieved by waveform engineering with the aid of good analog properties exhibited by the iron oxide-based memristor. The spike-time-dependence plasticity (STDP) occurs at moderate presynaptic firing frequencies and spike-rate-dependence plasticity (SRDP) dominates other regions. This demonstration provides a novel approach in neural coding implementation, which facilitates the development of bio-inspired computing systems.
[Show abstract][Hide abstract] ABSTRACT: The high leakage power due to process nodes scaling
down has been one of the critical issues in CMOS circuits,
especially the sleep power critical systems. The conventional
retention CMOS register based approaches cannot fully address
the high standby energy issue in long time standby systems.
The recent non-volatile Flip-Flop (nvFF) based approaches may
achieve zero sleep power consumption, but still face the challenges
of high saving power and area overhead, and low data reliability.
This paper presents a new resistive Non-Volatile Memory (NVM)
based circuit architecture with zero leakage power dissipation.
It stores the states of the registers in the localized spin-torquetransfer
magnetic random access memory (STT-MRAM) array
through scan chains, which has reduced by more than 20%
sleep energy than conventional nvFF schemes, and saved by
more than 99:8% sleep energy compared to the retention CMOS
register based approaches when the sleep time is longer than
1s. Moreover, the proposed pipelined quad-phase saving scheme
maximizes the saving speed, while reduces the peak saving
Circuits and Systems I: Regular Papers, IEEE Transactions on 04/2014; · 2.30 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The high leakage current has been one of the critical issues in SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories (NVMs) have been utilized to tackle the issue with their superior energy efficiency and fast power-on speed. Phase Change Memory (PCM) is one of the most promising resistive NVMs with the advantages of low cost, high density and high resistance ratio. However, most of the reported PCM-based FPGAs have significant active leakage power and reliability issues. This paper presents a low active leakage power and high reliability PCM based non-volatile SRAM (nvSRAM). The low active leakage power and high reliability are achieved by biasing PCM cells at 0 V during FPGA operation. Compared to the state-of-the-art, the proposed nvSRAM based 4-input look up table (LUT) achieves 174 times reduction in active leakage power and 15000 times increase in retention time. In addition, the proposed nvSRAM-based FPGA system significantly accelerates the loading speed to less than 1 ns with 2.54 fJ/cell loading energy.
Circuits and Systems I: Regular Papers, IEEE Transactions on 03/2014; · 2.30 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A compositionally matched superlattice-like (SLL) structure comprised of Ge2Sb2Te5 (GST) and nitrogen-doped GST (N-GST) was developed to achieve both low current and high endurance Phase Change Random Access Memory (PCRAM). N-GST/GST SLL PCRAM devices demonstrated ∼37% current reduction compared to single layered GST PCRAM and significantly higher write/erase endurances of ∼108 compared to ∼106 for GeTe/Sb2Te3 SLL devices. The improvements in endurance are attributed to the compositionally matched N-GST/GST material combination that lowers the diffusion gradient between the layers and the lower crystallization-induced stress in the SLL as revealed by micro-cantilever stress measurements.
[Show abstract][Hide abstract] ABSTRACT: A writing circuit for a resistive memory cell arrangement is provided, the resistive memory cell arrangement including a plurality of resistive memory cells. The writing circuit includes a controlled voltage source including a plurality of pass transistors, wherein each pass transistor includes a first source/drain terminal, a second source/drain terminal and a gate terminal, and wherein the first source/drain terminal is configured to be electrically coupled to a power supply line and the second source/drain terminal is configured to be electrically coupled to a bit line associated with a resistive memory cell of the plurality of resistive memory cells, and a plurality of switches, wherein each switch is configured to control the gate terminal of the pass transistor, wherein the controlled voltage source is configured to supply a voltage to the resistive memory cell for a write operation. Further embodiments provide a resistive memory cell arrangement.
[Show abstract][Hide abstract] ABSTRACT: TiWOx interfacial layer was proposed and implemented to act as both heater and inter-diffusion barrier for phase change memory through a complementary metal-oxide semiconductor compatible oxidization process. Significant reduction of RESET current was obtained due to more efficient Joule heating and better thermal confinement. About one order of magnitude endurance increase was achieved for the device with TiWOx due to suppression of inter-diffusion between Ge2Sb2Te5 and TiW. The change of the minimum RESET voltage against cycling was reduced by TiWOx layer with shorter RESET pulse, which would benefit device cyclability.
[Show abstract][Hide abstract] ABSTRACT: Thermal stability of 100 nm Ge2Sb2Te5 thin film during annealing from room temperature to 240 °C inside a UHV chamber was studied in situ by X-ray photoelectron spectroscopy (XPS) and ex situ by X-ray diffraction (XRD) and atomic force microscopy (AFM). Ge species are found to diffuse preferentially to the surface when GST film is annealed from 25 °C to 100 °C. This process is accompanied by a change of phase whereby the amorphous film completely becomes face-center-cubic (FCC) phase at 100 °C. From 100 °C to 200 °C, both Sb and Te species are observed to diffuse more to the surface. The FCC phase is partially changed into hexagonal-close-pack (HCP) phase at 200 °C. At 220 °C, FCC phase is completely transformed into HCP phase. Loss of Sb and Te are also detected from the surface and this is attributed to desorption due to their high vapor pressures. At 240 °C, Sb and Te species are found to have desorbed completely from the surface, and leave behind Ge-rich 3D droplets on the surface. The separation of Ge2Sb2Te5 into Sb,Te-rich phase and Ge-rich phase is thus the main mechanism to account for the failure of Ge2Sb2Te5-based phase change memory devices under thermal stress.
[Show abstract][Hide abstract] ABSTRACT: The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. Phase-change materials are highly promising in this respect. However, their contradictory speed and stability properties present a key challenge towards this ambition. We reveal that as the device size decreases, the phase-change mechanism changes from the material inherent crystallization mechanism (either nucleation- or growth-dominated), to the hetero-crystallization mechanism, which resulted in a significant increase in PCRAM speeds. Reducing the grain size can further increase the speed of phase-change. Such grain size effect on speed becomes increasingly significant at smaller device sizes. Together with the nano-thermal and electrical effects, fast phase-change, good stability and high endurance can be achieved. These findings lead to a feasible solution to achieve a universal memory.
[Show abstract][Hide abstract] ABSTRACT: Phase-change random access memory cells with superlattice-like (SLL) GeTe/Sb(2)Te(3) were demonstrated to have excellent scaling performance in terms of switching speed and operating voltage. In this study, the correlations between the cell size, switching speed and operating voltage of the SLL cells were identified and investigated. We found that small SLL cells can achieve faster switching speed and lower operating voltage compared to the large SLL cells. Fast amorphization and crystallization of 300 ps and 1 ns were achieved in the 40 nm SLL cells, respectively, both significantly faster than those observed in the Ge(2)Sb(2)Te(5) (GST) cells of the same cell size. 40 nm SLL cells were found to switch with low amorphization voltage of 0.9 V when pulse-widths of 5 ns were employed, which is much lower than the 1.6 V required by the GST cells of the same cell size. These effects can be attributed to the fast heterogeneous crystallization, low thermal conductivity and high resistivity of the SLL structures. Nanoscale PCRAM with SLL structure promises applications in high speed and low power memory devices.
[Show abstract][Hide abstract] ABSTRACT: Phase change random access memory (PCRAM) cells utilizing nickel monosilicide (NiSi) or platinum monosilicide (PtSi) as the
bottom electrode as well as a heater material was demonstrated. Electrical and simulation results demonstrate the feasibility
of employing silicides as a bottom electrode/heater in a PCRAM. The memory cells fabricated attained promising results such
as low programming currents and sufficient resistance ratio between the crystalline (SET) and amorphous (RESET) states. A
low RESET current of
and a SET current of
were obtained for contact dimensions of
, while a resistance ratio of 2 orders of magnitude could be achieved employing PtSi as the bottom electrode. This work therefore
enables the integration of PCRAM directly on the silicided drain regions of field effect transistors, facilitating compact
integration in complementary metal-oxide-semiconductor (CMOS) technology with reduced process complexity and cost.
Journal of The Electrochemical Society. 02/2011; 158(3):H232-H238.
[Show abstract][Hide abstract] ABSTRACT: A phase change memory device integrated with a nickel monosilicide (NiSi) bottom electrode and a dielectric (Ta2O5) interlayer was investigated. The presence of a low thermal conductivity thin film between the bottom electrode and phase change layer promotes heating efficiency in the device. Reset voltages down to 2.2 and 1.86 V could be achieved for memory device without and with the Ta2O5 interlayer, respectively. In addition, low reset current of 0.66 mA and SET current of 0.2 mA were obtained for devices with Ta2O5 interlayer having a contact dimension of ∼1 μm. Endurance of the devices was also studied.
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 01/2011; 29. · 1.36 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In this paper, we report a novel Cr/TaOx/Al (top to bottom) Resistive Random Access Memory (RRAM) which works as a bipolar switching device. The RRAM devices have demonstrated excellent memory performance including small magnitude of switching voltages (about 2 V), a tight distribution of Vset and Vreset, low switching current, large off/on resistance ratio R of up to 107, and good retention characteristics (more than 105 s) at high temperature (120°C). Resistance of both states shows little degradation, and retention characteristics can be extrapolated to 10 years. The relationship between active area and resistance at low resistance state is studied and the switching appears to be a local phenomenon which is likely to be of the filament type. Forming gas anneal has an additional positive effect on the device performance parameters, as it leads to smaller magnitude of switching voltages and better uniformity of the resistance in the high resistance state.
[Show abstract][Hide abstract] ABSTRACT: The thermal conductivity of nitrogen-doped Ge2Sb2Te5 (N-GST) was analyzed using Frequency Domain Thermoreflectance (FDTR). The thermal conductivity of amorphous N-GST (∼0.15 W/m-K) was not found to change significantly as the nitrogen concentration was raised from 0 at% to ∼6 at%, possibly due to the huge amount of phonon scattering in the disordered films. The thermal conductivity of crystalline N-GST films was found to increase initially with increasing N content, but then to decrease upon further N addition. X-ray diffraction spectra of N-GST films show increasing defect density that correlates with the decrease in thermal conductivity of the crystalline films at higher nitrogen content.
[Show abstract][Hide abstract] ABSTRACT: The energy band alignment between stoichiometric phase change alloys residing along the pseudobinary line of GeTe-Sb2Te3[(GeTe)x(Sb2Te3)1-x] and SiO2 was obtained employing high-resolution x-ray photoelectron spectroscopy. The valence band offsets were determined using both the core-level spectra and valence band spectra in the analysis. The results obtained show that the band offsets vary with the composition of the (GeTe)x(Sb2Te3)1-x alloy, exhibiting a parabolic dependence on the amount of GeTe in the alloy. Increasing the proportion of GeTe in the (GeTe)x(Sb2Te3)1-x alloy was generally found to increase (decrease) the valence band (conduction band) offsets, while the binary alloys (GeTe, Sb2Te3) have similar band offset values. This information could be useful for phase change memory device design and optimization.
[Show abstract][Hide abstract] ABSTRACT: Cleaning the surfaces of the as-deposited Ge2Sb2Te5 was studied by X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM) and X-ray diffraction (XRD). The mixed native oxides on the as-deposited Ge2Sb2Te5 surface can be easily removed by dipping Ge2Sb2Te5 in de-ionized water for 1min, while the surface morphology remains unchanged after cleaning. Native oxides only re-grow after exposure to air for more than 4min. Although dipping in water leads to a surface layer deficient in Ge and Sb, the surface composition of Ge2Sb2Te5 can recover to its stoichiometric value after annealing at 200°C in vacuum. The phase remains amorphous at room temperature after dipping in water, and changes to fcc and hcp after annealing at 100 and 220°C, respectively.
[Show abstract][Hide abstract] ABSTRACT: We study the dependence of the hole barrier height at the metal/α-Ge2Sb2Te5 interface as a function of nitrogen doping in Ge2Sb2Te5 as well as the vacuum work function of the metal. Materials parameters such as the band gap, dielectric constant, and electron affinity values of these nitrogen-doped films were also determined. All Ge2Sb2Te5 films studied in this work are amorphous. Following further physical analysis, the effective work functions of metals on nitrogen-doped Ge2Sb2Te5 films were obtained and found to differ from that of their values in vacuum. This led to the extraction of the slope parameter Sx and charge neutrality level ΦCNL which characterizes Ge2Sb2Te5. Appreciable metal Fermi-level pinning to the charge neutrality level of Ge2Sb2Te5, which is located near the valence band edge, was observed. We then demonstrate application of the extracted parameters to obtain the band alignment of α-Ge2Sb2Te5 with various other materials such as SiO2, giving good agreement with experimental results.
Journal of Applied Physics 09/2010; 108(5):053708-053708-7. · 2.19 Impact Factor