[show abstract][hide abstract] ABSTRACT: In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm <sup>Ø</sup>TSV, 5 μm thick polymer liner, 25-μm-Ø Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.
IEEE Transactions on Components, Packaging, and Manufacturing Technology 07/2011; · 1.26 Impact Factor
[show abstract][hide abstract] ABSTRACT: The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced highk/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5µm and via depth in the silicon substrate is 50µm. Dense structures have a pitch of 10µm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, Lake Buena Vista, FL; 05/2011
[show abstract][hide abstract] ABSTRACT: In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.
IEEE Journal of Solid-State Circuits 02/2011; · 3.06 Impact Factor
[show abstract][hide abstract] ABSTRACT: As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
[show abstract][hide abstract] ABSTRACT: Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This has been successfully demonstrated for the first time in a 300mm production line, and the compatibility of thin wafer handling with backside processing has been evaluated.
[show abstract][hide abstract] ABSTRACT: New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically connecting them in the vertical direction, and then forming a chip structure with significant advantages over traditional chips. However, before the 3D–stacking of IC’s becomes a mainstream process numerous metrology issues need to be solved. In this paper we discuss the critical in-line metrology needs during bonding and thinning of the device wafers before stacking. We show how TSV depth variations, glue layer defects and grinding issues require monitoring for a successful 3D integration.
[show abstract][hide abstract] ABSTRACT: In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers.
[show abstract][hide abstract] ABSTRACT: Thin wafer handling has become a very challenging topic of emerging 3D technologies, and temporary wafer bonding to a carrier support wafer is one way to guarantee the required mechanical stability and rigidity to the thin wafer during subsequent backside processing. The temporary bonding approach followed by Imec is based on the adhesive material HT10.10 from Brewer Science (WaferBond<sup>®</sup> HT-10.10). The thermal and chemical stability of the temporary adhesive layer has been fully assessed and characterized in a 300mm production line, and for the first time we report on the full integration of thin wafer handling with backside processing on 300mm CMOS wafers.
3D Systems Integration Conference (3DIC), 2010 IEEE International; 12/2010
[show abstract][hide abstract] ABSTRACT: We describe the design challenges for a low-cost 130nm 3D CMOS technology with 5μm diameter at 10μm pitch Cu-TSV. We investigate electrical, thermal and thermo-mechanical issues encountered in 3D. The electrical yield and ESD of TSVs is reviewed and designers are advised how to ensure yield and reliability. For thermal and thermo-mechanical we'll indicate based on experimental characterization, the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow which leverages information captured by smart samples.
[show abstract][hide abstract] ABSTRACT: 3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.
[show abstract][hide abstract] ABSTRACT: Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without TSVs. The stability of this structure was investigated by thermal cycling tests. Measurements after 1000 cycles between -55 and 125°C demonstrated good robustness of the stacked integrated circuit (SIC) structure. Residual stress induced by the TSVs was experimentally examined by micro-Raman spectroscopy. The results revealed that TSV induced stress is negligible for carrier mobility in this technology.
[show abstract][hide abstract] ABSTRACT: The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we'll indicate the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow hereto which leverages information captured by “smart mechanical samples” .
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on; 05/2010
[show abstract][hide abstract] ABSTRACT: In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using both Cu Through Silicon Vias (TSV) First and cost effective solution Die-to-Wafer Hybrid Collective bonding. The Cu TSV-First process is inserted between contact and M1. The top die is thinned down to 25 Â¿m and bonded to the landing wafer by Hybrid Bonding. Measurements and simulations of the power delay trade-offs of various 3D Ring Oscillator are provided as a demonstration of the relevance of such process route and of the design/simulation capabilities.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
[show abstract][hide abstract] ABSTRACT: Sub-surface hydrophilisation and an increase in effective k is known as damage to a highly porous ultra-low k (ULK) film when removing a metal layer from this ULK film by Chemical Mechanical Polishing (CMP). The degree of ULK hydrophilisation is linked to the amount and depth of scratches formed on the dielectric during polishing. To be able to trace key factors that could lead to a higher resistance against scratches, we looked into the root cause of scratch formation and how it relates to the type of overlaying metal film that we remove during the CMP step. Our work shows that the ULK scratch formation during CMP is linked to the formation of large metal-containing particles in the slurry on the pad. We were able to evidence and separate those particles and characterized them as silica-metal agglomerates. Those "harder" agglomerates are more detrimental to the ULK surface - i.e. more and deeper scratches are formed - when clearing Ta-based metal layers from the ULK film.
[show abstract][hide abstract] ABSTRACT: This article describes less explored solutions to improve interconnect performance without changing established steps (etch, strip, clean, CMP) in a sub-100nm integration route. Process conditions of the porogen-based low-k are adjusted by (1) varying the curing time (2) adding a thermal anneal step prior to CuO reduction or (3) depositing a capping layer on top of the low-k after curing. The low-k material examined in this study is Aurora® ELK HM (k∼2.5).The integration process was robust against these variations, showing good electrical yield for all process splits. RC-product was improved when using a shorter curing time and when an anneal step prior to CuO reduction was performed. The use of a thicker capping layer decreased capacitance, showing an improved protection against damage.
[show abstract][hide abstract] ABSTRACT: We investigate key design issues of a low-cost 3D Cu-TSV technology: impact of TSV on MOS devices and interconnect, reliability, thermal hot spots, ESD, signal integrity and impact on circuit performance. We experimentally verify their importance and propose changes in current design practices to enable low-cost systems.
IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010; 01/2010