[Show abstract][Hide abstract] ABSTRACT: In order to enable an oxide-free Cu-to-Cu bonding in a (dual) damascene process, 3-aminopropyltrimethoxysilane- and decanethiol-derived self-assembled monolayers are selectively deposited in a dielectric-Cu based metal–insulator–metal (MIM) capacitor used as a test vehicle, which represents a dual damascene architecture environment. A two-steps SAM coating sequence is investigated for this purpose. In a first step, a “sacrificial” SHSAM is deposited on the Cu areas at the bottom of the vias. In a second step, a “barrier” NH2SAM is deposited on the dielectric areas in the field region and via’s sidewalls. This deposition sequence followed by the selective thermal ablation of the “sacrificial” SAM vs. the “barrier” SAM, enable an oxide-free Cu-to-Cu connection at via’s bottom. The differential in thermal stability between the amino and thiol SAMs has been studied by water contact angle and cyclic voltammetry. While the sacrificial SAM is selectively desorbed by thermal ablation already at ∼200 °C, the barrier SAM on the dielectric sidewall and field regions withstands a thermal budget as high as ∼350 °C. The substrate-selective SAMs depositions are revealed by XPS chemical characterization on the Cu and dielectric areas of the MIM structures supported by the SEM visualization of the Au nanoparticles that selectively decorate the NH2 functionalities of the barrier SAM.
[Show abstract][Hide abstract] ABSTRACT: Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400 °C range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. TSV aspect ratios can vary as function of the integration scheme, for instance in a via-last or via-middle flow, and thus barrier continuity requires conformality which guarantees the presence of a diffusion barrier until the bottom of the TSV. Target conformality can either be obtained by PVD, typically for TSV A.R. ⩽ 10:1. We report on the thermal stability of Ta, and Ti barriers and we show that 5 nm PVD Ta barriers are thermally stable, while PVD Ti-barriers require thicknesses above 5 nm to guarantee their thermal stability.
[Show abstract][Hide abstract] ABSTRACT: Power and substrate domains are strategically isolated or unified in heterogeneous 3D integration. In-tier probing circuitry provides accessibility to power delivery and substrate networks in a deep tier of a 3D chip stack and capability of diagnosing intra/inter tier coupling. A two-tier demonstrator was successfully tested in a 130 nm CMOS, 3D-SIC Cu TSV technology.
3D Systems Integration Conference (3DIC), 2011 IEEE International; 01/2012
[Show abstract][Hide abstract] ABSTRACT: In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm <sup>Ø</sup>TSV, 5 μm thick polymer liner, 25-μm-Ø Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.
IEEE Transactions on Components, Packaging, and Manufacturing Technology 07/2011; · 1.26 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers.
[Show abstract][Hide abstract] ABSTRACT: The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300 mm industry-compliant via-middle TSV module, integrated to an advanced highk/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5 µm and via depth in the silicon substrate is 50 µm. Dense structures have a pitch of 10 µm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65 nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, Lake Buena Vista, FL; 05/2011
[Show abstract][Hide abstract] ABSTRACT: In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.
IEEE Journal of Solid-State Circuits 02/2011; · 3.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
[Show abstract][Hide abstract] ABSTRACT: Two different material-selective Self assembled monolayers (SAMs) were successfully deposited on Cu and SiO2 structures that mimic the Dual Damascene integration scheme. A two-step SAM coating process is presented. First, a “sacrificial” SAM is deposited at the Cu bottom and secondly, a “barrier” SAM at the SiO2 surface. The order in the SAMs deposition sequence and the differential thermal release of the thiol “sacrificial” SAM vs. the amino “barrier” SAM, allows an oxide-free Cu-to-Cu connection at the vias bottom. While the sacrificial SAM is selectively released by thermal ablation, the barrier SAM remains intact on the dielectric sidewall and field regions, ready for the subsequent copper metallization.
[Show abstract][Hide abstract] ABSTRACT: Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This has been successfully demonstrated for the first time in a 300mm production line, and the compatibility of thin wafer handling with backside processing has been evaluated.
Proceedings - Electronic Components and Technology Conference 01/2011;
[Show abstract][Hide abstract] ABSTRACT: New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically connecting them in the vertical direction, and then forming a chip structure with significant advantages over traditional chips. However, before the 3D–stacking of IC’s becomes a mainstream process numerous metrology issues need to be solved. In this paper we discuss the critical in-line metrology needs during bonding and thinning of the device wafers before stacking. We show how TSV depth variations, glue layer defects and grinding issues require monitoring for a successful 3D integration.
Proceedings - Electronic Components and Technology Conference 01/2011;
[Show abstract][Hide abstract] ABSTRACT: In this paper, we report on the development of Cu pillars and their impact on the subsequent thinning process for 3D applications. As the Cu pillars have a height of tens of microns (typically between 50–100µm), controlling the total thickness variation (TTV) after wafer thinning is becoming even more challenging. The Cu pillars are processed after completion of the Back End of Line (BEOL) with a target thickness of 50µm for a diameter of 80µm and a pitch of 200µm. The key challenge for D integration is the control of the wafer TTV after back grinding in order to allow TSV reveal. After optimization of the temporary wafer bonding in presence of high topography induced by 50µm high Cu pillars, a TTV after thinning below 5µm is achieved, which is comparable to the TTV obtained after wafer thinning without topography.
[Show abstract][Hide abstract] ABSTRACT: Barrier reliability in 3D Through-Si Via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400°C range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. We report on the thermal stability of Ta and Ti barriers and we show that 5nm Ta barriers are thermally stable, while Ti-barriers require thicknesses above 5nm to guarantee their thermal stability.
Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International; 01/2011
[Show abstract][Hide abstract] ABSTRACT: Thin wafer handling has become a very challenging topic of emerging 3D technologies, and temporary wafer bonding to a carrier support wafer is one way to guarantee the required mechanical stability and rigidity to the thin wafer during subsequent backside processing. The temporary bonding approach followed by Imec is based on the adhesive material HT10.10 from Brewer Science (WaferBond<sup>®</sup> HT-10.10). The thermal and chemical stability of the temporary adhesive layer has been fully assessed and characterized in a 300mm production line, and for the first time we report on the full integration of thin wafer handling with backside processing on 300mm CMOS wafers.
3D Systems Integration Conference (3DIC), 2010 IEEE International; 12/2010
[Show abstract][Hide abstract] ABSTRACT: We describe the design challenges for a low-cost 130nm 3D CMOS technology with 5μm diameter at 10μm pitch Cu-TSV. We investigate electrical, thermal and thermo-mechanical issues encountered in 3D. The electrical yield and ESD of TSVs is reviewed and designers are advised how to ensure yield and reliability. For thermal and thermo-mechanical we'll indicate based on experimental characterization, the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow which leverages information captured by smart samples.
[Show abstract][Hide abstract] ABSTRACT: 3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.
[Show abstract][Hide abstract] ABSTRACT: Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without TSVs. The stability of this structure was investigated by thermal cycling tests. Measurements after 1000 cycles between -55 and 125°C demonstrated good robustness of the stacked integrated circuit (SIC) structure. Residual stress induced by the TSVs was experimentally examined by micro-Raman spectroscopy. The results revealed that TSV induced stress is negligible for carrier mobility in this technology.
[Show abstract][Hide abstract] ABSTRACT: The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we'll indicate the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow hereto which leverages information captured by “smart mechanical samples” .
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on; 05/2010
[Show abstract][Hide abstract] ABSTRACT: This article describes less explored solutions to improve interconnect performance without changing established steps (etch, strip, clean, CMP) in a sub-100nm integration route. Process conditions of the porogen-based low-k are adjusted by (1) varying the curing time (2) adding a thermal anneal step prior to CuO reduction or (3) depositing a capping layer on top of the low-k after curing. The low-k material examined in this study is Aurora® ELK HM (k∼2.5).The integration process was robust against these variations, showing good electrical yield for all process splits. RC-product was improved when using a shorter curing time and when an anneal step prior to CuO reduction was performed. The use of a thicker capping layer decreased capacitance, showing an improved protection against damage.