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ABSTRACT: Infrequent dynamic events like V<sub>CC</sub> droops and temperature changes result in the use of a static V<sub>CC</sub> guardband in 8T SRAM arrays. This paper proposes the use of tunable replica bits (TRBs) as a potential solution to mitigating a part of the V<sub>CC</sub> guardband. Measured data on a 16 KB 8T array featuring tun able replica bits illustrate 9% reduction of the operating minimum V<sub>CC</sub> (V<sub>MIN</sub>) and correspondingly a 7.5% reduction in array power.
IEEE Journal of Solid-State Circuits 05/2011; · 3.23 Impact Factor
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K.A. Bowman,
J.W. Tschanz,
S.L. Lu,
P.A. Aseron,
M.M. Khellah, A. Raychowdhury,
B.M. Geuskens,
C. Tokunaga,
C.B. Wilkerson,
T. Karnik,
V.K. De
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ABSTRACT: A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (F<sub>CLK</sub>) guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the Fclk guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (V<sub>CC</sub>) measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency V<sub>CC</sub> droops. The microprocessor core also supports two separate error-recovery techniques to guarantee correct execution even if dynamic variations persist. The first technique requires clock control to replay errant instructions at 1/2F<sub>CLK</sub>. In comparison, the second technique is a new multiple-issue instruction replay design that corrects errant instructions with a lower performance penalty and without requiring clock control. Silico-
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n measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% V<sub>CC</sub> droop. In addition, the microprocessor includes a new adaptive clock control circuit that interfaces with the resilient circuits and a phase-locked loop (PLL) to track recovery cycles and adapt to persistent errors by dynamically changing Fclk f°Γ maximum efficiency.
IEEE Journal of Solid-State Circuits 02/2011; · 3.23 Impact Factor
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ABSTRACT: A 45nm microprocessor integrates an all-digital dynamic variation monitor (DVM), consisting of a tunable replica circuit with a time-to-digital converter, to measure the impact of dynamic variations on path-level delay or frequency. Measurements reveal the high sensitivity of the microprocessor maximum clock frequency (F<sub>MAX</sub>) to the placement and magnitude of a high-frequency supply voltage (V<sub>CC</sub>) droop and demonstrate the DVM capability of tracking F<sub>MAX</sub> changes to within 1% for a wide range of V<sub>CC</sub> droop profiles. Furthermore, the DVM interfaces with an adaptive clock control circuit to dynamically change the clock frequency in response to dynamic variations, enabling the microprocessor to operate at maximum efficiency.
Custom Integrated Circuits Conference (CICC), 2010 IEEE; 10/2010
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ABSTRACT: The paper presents a RD disturb model study of STT-MTJ memory bits. It shows that high-current short-pulsed RD may cause failure under hammer conditions. Analytical models for such have been developed and validated against numerical simulations.
Device Research Conference (DRC), 2010; 07/2010
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ABSTRACT: A 16 KB 8T register-file macro in a 45 nm CMOS process uses on-die PVT-adaptive boosting of read- and write-wordline for minimizing V<sub>MN</sub> while reducing boosting overhead for maximum power benefit. Measurements of 1 MB 8T arrays in a single-VCC ¿mP core indicate 6 to 27% lower power for arrays access variations of 10% (75 pF) to 30% (1 nF).
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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J. Tschanz,
K. Bowman,
Shih-Lien Lu,
P. Aseron,
M. Khellah, A. Raychowdhury,
B. Geuskens,
C. Tokunaga,
C. Wilkerson,
T. Karnik,
V. De
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ABSTRACT: A 45 nm 1.3 GHz microprocessor core employs error-detection circuits, tunable replica circuits, and error-recovery circuits, to mitigate dynamic variation guardbands for maximum throughput. An adaptive clock controller adjusts the frequency based on error statistics to optimize efficiency. Silicon measurements show resilient operation as well as throughput gains of 12 to 16% at 1.0 V and 22 to 23% at 0.8 V.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
