Publications (3)0 Total impact
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ABSTRACT: Since the first 3b/cell (X3) NAND flash memory paper in ISSCC 2008 , market demand for applications using high-density low-cost flash memory such as tablets, smart phones, and SSDs, has increased rapidly. Various electronic devices already use X3 NAND. The use of all BL (ABL) architecture, advanced circuitry, and enhanced algorithms enables this work to achieve 18MB/s performance, allowing penetration of markets where 2b/cell (D2) NAND has been used. As NAND memory scales aggressively towards 10nm, achieving the same level of performance with X3 chips is increasingly difficult. This paper addresses challenges with improvements made over previous NAND generations to achieve high performance while maintaining a low fail-bit count (FBC) and cost savings from an improved architecture and tightly packed peripheral circuits. Air gap [2,3] technology further improves write throughput by reducing neighbor interference and WL RC. A toggle mode 400Mb/s I/O interface reduces system overhead and enhances overall performance.
Conference Paper: A 113mm2 32Gb 3b/cell NAND flash memory[Show abstract] [Hide abstract]
ABSTRACT: NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased and NAND flash memories are enabling a wide range of new applications. In such situations, to achieve larger capacity at low cost per bit, technical improvement in feature-size scaling, multi-bit per cell and area reduction are essential. To respond to such continuous requirements of cost reduction and density increase, 32 Gb 3 b/cell (D3) NAND flash memory with sub-35 nm CMOS process is developed. Introduction of sub-35 nm CMOS process and D3 technology doubles the capacity at almost the same chip area compared to previously published 43 nm 16 Gb 2 b/cell (D2) chip and about 80% chip area compared to previously published 56 nm 16 Gb D3 chip. The chip of size 9.215 x 12.247 mm2 = 112.86 mm2 enables the 32 Gb chip to fit in a microSD memory card. The chip architecture has 2 planes with 1.4 K blocks/plane, 1.5 MB block size and 8 KB page size. The block consists of 66 wordlines (WLs) containing 2 dummy WLs between select gates (SGs). All memory cells on the same WL have 3 pages and can be programmed and read simultaneously.IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009
Conference Paper: A 16Gb 3b/ Cell NAND flash memory in 56nm with 8MB/s write rate[Show abstract] [Hide abstract]
ABSTRACT: We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added in D3 devices, the 16 Gb D3 chip in this paper achieves 0.112 Gb/mm<sup>2</sup> compared to 0.079 Gb/mm<sup>2</sup> on D2 chips, as previously reported (K. Takeuchi et al.,2006). This is a 41% improvement in Gb/mm<sup>2</sup> and a 20% gain in overall die-size.Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008