V. Honkote

Drexel University, Philadelphia, Pennsylvania, United States

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Publications (15)2.28 Total impact

  • Vinayak Honkote, Baris Taskin
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    ABSTRACT: Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal ${\pm} $1.5% change in the tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1–R5 and ISPD 2010 benchmark circuits.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2012; 20(8):1528-1532. · 1.14 Impact Factor
  • Vinayak Honkote, Ankit More, Baris Taskin
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    ABSTRACT: Resonant rotary clocking is a high-frequency, low-power technology for high performance integrated circuits (IC). The implementation of the rotary clocking technology requires long interconnects with varying geometric shape segments on the chip, which are modeled by transmission lines. The parasitics exhibited by the transmission line interconnects play a major role in characterizing the high frequency operation. To this end, the impact of parasitics on the operating characteristics of the rotary rings due to the different interconnect segments are identified. The interconnect parasitics are analyzed using a 3D finite element method based full wave electromagnetic analysis. Simulations performed for the rotary ring with 3D full wave based parasitic analysis results in 23.68% reduced clock frequency when compared with a conventional 2D based parasitic analysis. The power dissipated on the rotary ring simulated using the 3D full wave based parasitic analysis is around 84% less than the clock tree and is within 5% of the power dissipated on the ring simulated using the 2D based parasitic analysis.
    Proceedings of the IEEE International Conference on VLSI Design 01/2012;
  • Vinayak Honkote, Baris Taskin
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    ABSTRACT: Rotary clocking is a resonant clocking technology for clock network design and distribution in high performance digital VLSI circuits. Rotary clocking technology offers an attractive alternative to the conventional clocking with high frequency clock signal generation at a low power dissipation rate. Traditionally, rotary clocking has been implemented using a regular array (grid) topology called rotary oscillatory arrays (ROA). In this paper, a custom rotary oscillatory array (CROA) topology is proposed for the generation and distribution of rotary clocking. The issues related to timing closure are addressed and the simulation-based analysis of the custom rotary rings is presented. The CROA design methodology is tested on the IBM R1-R5 benchmark circuits. Compared to the traditional ROA, custom ROA results in 39.25% of tapping wirelength savings. The parasitic effects due to the customization of the topology - computed with partial element equivalent circuit (PEEC) analysis - are incorporated and the CROA topologies are simulated in SPICE. The simulation results show that, with additional parasitics due to the topological factors, the resultant clock frequency is observed to be 8.79% slower (assuming the tapping wirelength remains the same) than the expected frequency of operation without considering the topological factors.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2011; · 1.14 Impact Factor
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    ABSTRACT: A novel rotary clock network routing method is proposed for the low-power resonant rotary clocking technology which guarantees: 1. The balanced capacitive load driven by each of the tapping points on the rotary rings, 2. Customized bounded clock skew among all the registers on chip, 3. A sub-optimally minimized total wirelength of the clock wire routes. In the proposed method, a forest of steiner trees is first created which connects the registers so as to achieve zero skew and greedily balance the total capacitance of each tree. Then, a balanced assignment of the steiner trees to the tapping points is performed to guarantee a balanced capacitive load on the rotary network. The proposed routing method is tested with the ISPD clock network contest and IBM r1-r5 benchmarks. The experimental results show that the capacitive load imbalance is very limited. The total wirelength is reduced by 64.2% compared to the best previous work known in literature through the combination of steiner tree routing and the assignment of trees to the tapping points. The average clock skew simulated using HSPICE is only 8.8ps when the bounded skew target is set to 10.0ps.
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011; 04/2011
  • V. Honkote, B. Taskin
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    ABSTRACT: Rotary clocking is a traveling wave based high-speed resonant clocking technology with low-power and controllable-skew properties. Capacitive load balance and bounded clock skew are identified as the primary requirements to maintain a stable oscillation frequency across the rings and to achieve timing closure, respectively, in the rotary oscillatory array (ROA). Towards this end, two methodologies are proposed to achieve balanced capacitive loads across the rings of the ROA with a bounded skew constraint. Experiments performed on IBM R1-R5 benchmark circuits show a 5.62X improved capacitive balance and a 3.67% improved clock skew to a total skew of 6.55% of the clock period at 1.8GHz. SPICE simulations show that the frequency variation across the rings of the ROA is reduced from 10.14% to 2.12% as well. Power dissipated with the proposed optimization methodologies are within ±1.5% of the conventional design automation techniques for rotary synchronization.
    Computer Design (ICCD), 2010 IEEE International Conference on; 11/2010
  • V. Honkote
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    ABSTRACT: Resonant rotary clocking is a next generation clocking technology for ultra-low power, multi-GHz range operation. Previous works demonstrate the feasibility of this technology with full-custom, low-complexity circuit implementations. In this work, the rotary operational principles are investigated at a larger scale, and physical design and timing verification methods are developed as a blueprint for a fully-automated, semi-custom implementation.
    VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on; 08/2010
  • V. Honkote, B. Taskin
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    ABSTRACT: The square wave generated from the rotary operation with adiabatic switching is a continuously traveling wave, which provides multiple phases of the clock signal on the rotary ring. Recent research in the design automation of rotary clocking implementation has adopted some simplifications of the phase assignments for scalability. Towards this end, the design techniques, employed in conventional IC flows, can be employed for rotary clock automation as well. In this work, a timing framework is developed and skew analysis is presented for the rotary clocking technology to observe the effects of certain design simplifications in timing automation. Further, a methodology is presented to achieve a bounded skew implementation for rotary clocking technology. Experiments performed on R1-R5 benchmark circuits show a negligible increase in wirelength (around 1.25%) for the bounded skew constraint implementation with a 3.5% skew bound, where as, without the bounded skew, overall skew would be 5.5%.
    Quality Electronic Design (ISQED), 2010 11th International Symposium on; 04/2010
  • Vinayak Honkote, Baris Taskin
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    ABSTRACT: Resonant rotary clocking is a low power-high speed clock distribution technology for the modern VLSI circuits. Alternative topological implementations of rotary clocking with non-regular custom rings have been proposed in literature. In this paper, the impact of parasitics of the non-regular topological geometries on the rotary operating characteristics is presented. In particular, partial element equivalent circuit (PEEC) analysis is used to show that the corner geometry in a custom ring increases the mutual inductance approximately by 80%. Also, SPICE simulations are performed where the parasitics due to the topological factors are incorporated for an 8% increased accuracy in simulation. Further, the power dissipation on the rotary ring is analyzed with varying number of corners. When tested with the IBM R1-R5 benchmark circuits, the total power dissipated on a custom ring (corners between 4 and 12) is within ±5% of the total power dissipated on a regular ring(4 corners).
    Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010; 01/2010
  • Vinayak Honkote, Baris Taskin
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    ABSTRACT: The high frequency of the rotary clocking technology is often susceptible to implementation parameters such as the variation in the total capacitive load distribution between the rings. SPICE simulations performed on the rotary rings with unbalanced capacitive load distribution show a 30.31% variation in the simulated frequencies across the rings. To address this problem, two novel methodologies called OCLB and SOCLB, are formulated for the optimal capacitive load balancing and sub-optimal capacitive load balancing with minimized wirelength, respectively. SPICE simulations performed with OCLB show 0.30% variation in the simulated frequencies across the rings. Further, SOCLB results in an average wirelength improvement of 69.24% over OCLB with a relatively balanced capacitive load distribution. SPICE simulations performed with SOCLB show 2.40% variation in the simulated frequencies across the rings, improved significantly over the 30.31% variation of the unbalanced case.
    VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010; 01/2010
  • V. Honkote, B. Taskin
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    ABSTRACT: Resonant clocking technologies have gained increased attention due to their superiority of clock frequency, power dissipation and variation tolerance. Existing research on resonant standing wave and rotary clocking technologies have improved the tapping wirelength and the balance in the capacitive load. In this paper, a design automation scheme for the skew analysis of standing wave and rotary clocking is presented. The analysis considering capacitive balancing demonstrates the trends in the skew mismatch for both standing wave and rotary clocking technologies (20.56% and 3.05% of the clock signal period), proving the rotary clocking technology to be more favorable for a low skew application.
    SoC Design Conference (ISOCC), 2009 International; 12/2009
  • Vinayak Honkote, Baris Taskin
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    ABSTRACT: Resonant clocking technologies have been gaining increased attention due to their superiority of clock frequency, power dissipation, and variation tolerance. Two of the resonant clocking technologies, standing wave and rotary clocking, require specialized clock routing procedures to accommodate grid-type distribution topologies and the tapping of registers onto these grids. The total tapping wirelength for both technologies are significant due to the impacts on power dissipation and routing congestion. A quantitative study is performed to compare the total tapping wirelengths for equivalent implementations of these two resonant clocking technologies. Experiments demonstrate that the standing wave technology (with mobius implementation) requires on average 3.99X less tapping wirelength compared to the rotary resonant clocking technology.
    Midwest Symposium on Circuits and Systems 08/2009;
  • Vinayak Honkote, Baris Taskin
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    ABSTRACT: Resonant clocking technologies are the next generation clocking technologies with GHz range frequency generation and effective power reduction features. The resonant standing wave oscillator technology (with mobius implementation) combines the advantages of resonant traveling wave oscillator and the traditional resonant standing wave oscillator. The high frequency in the mobius standing wave oscillator implementation is often susceptible to implementation parameters such as the variation in the total capacitive load distribution between the rings topology. In this paper, a novel capacitive load balancing methodology is presented for the mobius implementation of resonant standing wave oscillator. The experiments performed on the IBM R1-R5 benchmark circuits demonstrate an average improvement of 4.66X in capacitive load balancing.
    Midwest Symposium on Circuits and Systems 08/2009;
  • V. Honkote, B. Taskin
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    ABSTRACT: Rotary clocking is a resonant clocking technology that provides a low-power, low-jitter clock signal with controllable skew. Due to the "rotary" traveling of the clock signal on the ring interconnect, each location on the rotary ring network leads to a different clock phase. Consequently, one of the features of the rotary clocking technology is the inherent non-zero clock skew operation. In this paper, it is shown that zero clock skew circuits can also be efficiently implemented with rotary clock synchronization. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal plusmn1.5% change in the tapping wirelength is reported in experiments on R1-R5 benchmark circuits.
    Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design; 04/2009
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    V. Honkote, B. Taskin
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    ABSTRACT: Timing closure and power envelopes for contemporary multi-core chips with high speed clock networks make the clock distribution design a challenging task. Resonant rotary clocking is a novel clocking technology for multi-gigahertz rate clock generation that provides minimal power dissipation. Rotary clocking implementations can easily provide independent synchronization of multiple cores as well. The traditional rotary clock design involves a regular array topology of oscillatory rings. In this paper, the rotary clock networks are designed and implemented using a custom ring topology. Custom ring topologies are advantageous as they reduce the total tapping wirelength for the registers tapping onto the oscillatory rings. A maze router based algorithm is developed for the implementation of custom topology rotary rings. In experiments performed on UCLA IBM R1-R5 benchmark circuits with the Elmore delay model, an improvement of 11.04% for register tapping wirelength is achieved on average.
    Computer Design, 2008. ICCD 2008. IEEE International Conference on; 11/2008
  • V. Honkote, B. Taskin
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    ABSTRACT: Resonant rotary clocking is a novel clocking technology for low power, high frequency integrated circuits. Rotary clock distribution networks are traditionally designed using regular array topologies of oscillatory rings. In this paper, the design of rotary clock distribution networks using a custom ring topology is investigated. Custom ring topologies permit reduced total wirelength for registers tapping onto the oscillatory rings, impacting overall power dissipation. A maze router based algorithm is developed for implementation of custom topology rotary rings. In experiments performed on UCLA IBM benchmark circuits, an improvement of 13.09% for register tapping wirelength is achieved on average.
    Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on; 09/2008